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f4781d3b1d76d797e77bdb5415e9f5335e491b98
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3 Commits

Author SHA1 Message Date
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Omar Chebib
b6a450f824 panic: Add support for SoC-level panic 
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
 2020-12-31 15:46:17 +08:00
Angus Gratton
7c08be5771 hal: Add initial ESP32-C3 support 
From internal commit 7761d6e8
 2020-11-30 15:23:15 +11:00