8 Commits

Author	SHA1	Message	Date
Nebojsa Cvetkovic	d0ceef20f4	refactor(xtensa): Rename specreg.h register macros ... This commit renames all registers in xtensa/specreg.h to by adding the prefix XT_REG_. This is done to avoid naming collisions with similar variable names. A new register file, viz., xt_specreg.h is created. The previous names are still available to use but have been deprecated. Closes https://github.com/espressif/esp-idf/issues/12723 Merges https://github.com/espressif/esp-idf/pull/16040	2025-06-17 15:37:33 +02:00
Renz Bagaporo	1efdcd69d9	xtensa: move out trax	2021-02-26 19:45:48 +08:00
Angus Gratton	66fb5a29bb	Whitespace: Automated whitespace fixes (large commit) ... Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)	2020-11-11 07:36:35 +00:00
Michael (XIAO Xufeng)	5425ef4ee4	hal: extract hal component from soc component	2020-09-01 13:25:32 +08:00
Renz Christian Bagaporo	c9a51bfbb2	soc: create abstraction for cpu related operations	2020-02-27 07:14:19 +05:00
Ivan Grokhotkov	8fec484d2b	xtensa: add TRAX support for esp32s2	2020-02-19 14:02:14 +01:00
morris	f5b03c9ea3	misc adjustment of esp32 component	2019-04-03 19:57:46 +08:00
morris	dbdb299bb1	create xtensa component ... 1. move xtensa specific files out of esp32 component 2. merge xtensa-debug-module component into xtensa	2019-03-27 20:24:28 +08:00