Laukik Hase
340de9823a
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-08-13 14:08:59 +05:30
armando
7a1e5f540e
feat(cache): supported cache panic driver on h4
2025-08-04 17:03:34 +08:00
Song Ruo Jing
48233e0e7e
refactor(ledc): remove deprecated LEDC_USE_RTC8M_CLK macro for v6.0
2025-07-30 20:01:47 +08:00
Song Ruo Jing
f61e780f60
refactor(clk): deprecate rtc_cal_sel_t enum
2025-07-30 20:01:46 +08:00
Song Ruo Jing
07120c1d38
remove(clk): remove RTC_CLK_SRC_INT_RC32K option for C6 (v6.0)
2025-07-30 20:01:46 +08:00
Mahavir Jain
22adc7ed75
Merge branch 'feat/secure_boot_ecdsa_p384' into 'master'
...
Support Secure Boot using ECDSA-P384 curve
Closes IDF-10016, IDF-10221, and IDF-12990
See merge request espressif/esp-idf!38517
2025-07-24 11:59:59 +05:30
Wu Zheng Hui
6f8dbe8a89
Merge branch 'fix/fix_submode_assert_in_slowck_changed_ota' into 'master'
...
fix(esp_hw_support): fix assert when changing 8MD256 RTC slow clock source during OTA
Closes PM-478
See merge request espressif/esp-idf!40292
2025-07-22 11:33:32 +08:00
harshal.patil
4fc9fd4891
fix(esp_system): Remove redundant crypto clock source selection
2025-07-21 09:19:42 +05:30
wuzhenghui
d7e1a747a6
fix(esp_hw_support): enable ESP_SLEEP_RTC_FAST_USE_XTAL_MODE only once in RTC_FAST selection
2025-07-18 15:29:07 +08:00
armando
84ae601fef
feat(cache): msync driver support on h4
2025-07-18 01:15:06 +00:00
Marius Vikhammer
296bc7ddcc
Merge branch 'feature/h4_reset_reasons' into 'master'
...
feat(system): updated H4 reset reasons
Closes IDF-12307
See merge request espressif/esp-idf!40499
2025-07-17 10:10:28 +08:00
Marius Vikhammer
374b31049b
feat(system): updated H4 reset reasons
2025-07-11 09:24:57 +08:00
Song Ruo Jing
b3fd9b6afa
fix(clk): XTAL_X2 clock is not usable on H21 MPW and H4 BETA5
2025-07-10 16:35:58 +08:00
Song Ruo Jing
caa382047b
fix(clk): ESP32H21 uses RC_SLOW_D4 as RTC slow clock
2025-07-10 16:35:58 +08:00
Song Ruo Jing
28df79aee8
feat(clk): Add basic clock support for esp32h4
2025-07-10 16:35:53 +08:00
morris
c4d7b1cfce
refactor(uart)!: deprcated esp_rom_uart.h
2025-07-08 18:56:17 +08:00
wuzhenghui
5436d1f0c4
fix(esp_system): force enable uart0 sclk in esp_restart
2025-06-27 20:04:13 +08:00
Alexey Lapshin
1a464c0914
fix(esp_system): suppress -Wanalyzer-infinite-loop warning
2025-06-25 18:00:39 +07:00
Konstantin Kondrashov
ff53d5d32c
Merge branch 'feature/iram_esp_system' into 'master'
...
feat(esp_system): Adds Kconfigs to place code in IRAM
Closes IDF-11426
See merge request espressif/esp-idf!38292
2025-06-24 05:46:09 +08:00
Konstantin Kondrashov
ff0408c087
feat(esp_system): Adds Kconfigs to place code in IRAM
2025-06-23 13:23:33 +03:00
yanzihan@espressif.com
08eea3c058
feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32p4
2025-06-23 00:28:53 +08:00
Sudeep Mohanty
7023f5bf3c
Merge branch 'contrib/github_pr_16040' into 'master'
...
refactor(xtensa): Rename specreg.h register macros (GitHub PR)
Closes IDFGH-11606 and IDFGH-15386
See merge request espressif/esp-idf!39649
2025-06-20 08:51:33 +02:00
Wu Zheng Hui
8ab969db1c
Merge branch 'bugfix/esp32c6_src_clk_label' into 'master'
...
clk: esp32c6: rename modem clock source selection
See merge request espressif/esp-idf!39756
2025-06-17 22:01:33 +08:00
Nebojsa Cvetkovic
d0ceef20f4
refactor(xtensa): Rename specreg.h register macros
...
This commit renames all registers in xtensa/specreg.h to by adding the
prefix XT_REG_. This is done to avoid naming collisions with similar
variable names. A new register file, viz., xt_specreg.h is created. The
previous names are still available to use but have been deprecated.
Closes https://github.com/espressif/esp-idf/issues/12723
Merges https://github.com/espressif/esp-idf/pull/16040
2025-06-17 15:37:33 +02:00
Song Ruo Jing
6d293c8582
feat(clk): Add basic clock support for esp32h21
2025-06-16 15:05:32 +08:00
Sylvio Alves
044de64f5b
fix(esp_system): rename modem clock source selection
...
Make sure to use proper label for modem source selection.
This does not fix any issue.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com >
2025-06-10 20:03:06 +08:00
Laukik Hase
0d8a1f5427
refactor(hal): Refactor the APM LL/HAL APIs
2025-06-06 18:28:47 +05:30
wuzhenghui
113f40a3e0
feat(esp_hw_support): support gate PLL div clock source by reference count
2025-05-27 19:55:23 +08:00
wuzhenghui
34f249a28b
feat(esp_hw_support): support esp_perip_clk_init for esp32c5
2025-05-27 19:55:22 +08:00
harshal.patil
e08189f37b
fix(system_internal): Avoid the sec clock reset caused due to resetting all crypto peripherals
2025-05-22 16:01:02 +05:30
Laukik Hase
12e2df2d74
feat(esp_tee): Support for ESP32-H2 - the rest of the components
2025-05-20 16:31:23 +05:30
chaijie@espressif.com
24c46f1b89
refactor: move_ocode_to_pmu_init_c6_c5_c61
2025-05-20 11:08:35 +08:00
armando
0c6aeecde4
feat(cache): supported cache panic driver on h21
2025-05-14 11:37:30 +08:00
armando
acda9a7a7e
feat(cache): supported cache driver on h21
2025-05-14 11:37:30 +08:00
harshal.patil
46225a4026
feat(esp_psram): Add a new API to just detect and enable the PSRAM
...
- esp_psram_chip_init() just detects and does basic initialisations of PSRAM
- esp_psram_init() initialises and maps/loads the PSRAM pages
2025-04-29 11:48:27 +05:30
Marius Vikhammer
298da837fd
feat(system): updated reset reasons for H21
2025-04-27 16:11:24 +08:00
Mahavir Jain
e37c47f6e7
Merge branch 'bugfix/crypto_reset_on_exit' into 'master'
...
fix(esp_system): reset crypto peripherals before device restart
See merge request espressif/esp-idf!38399
2025-04-17 21:24:25 +08:00
Laukik Hase
4a4d63d36e
feat(esp_tee): Protect the ECC peripheral from REE access
2025-04-16 19:19:04 +05:30
Laukik Hase
fc4802c0d6
feat(esp_tee): Protect the HMAC and DS peripherals from REE access
2025-04-16 19:19:04 +05:30
Mahavir Jain
55a2ad3df3
fix(esp_system): reset crypto peripherals before device restart
...
This change addresses a rare but critical issue observed on certain
ESP32-C3 and ESP32-S3 devices, where secure boot verification
intermittently fails due to improper cleanup of crypto peripherals
during a restart.
Background – Restart Behavior in IDF
------------------------------------
In ESP-IDF, when the device restarts (via `esp_restart()` or due to a
panic/exception), a partial peripheral reset is performed followed by a
CPU reset. However, until now, crypto-related peripherals were not
included in this selective reset sequence.
Problem Scenario
----------------
If a restart occurs while the application is in the middle of a bignum
operation (i.e., using the MPI/Bignum peripheral), the ROM code may
encounter an inconsistent peripheral state during the subsequent boot.
This leads to transient RSA-PSS secure boot verification failures.
Following such a failure, the ROM typically triggers a full-chip reset
via the watchdog timer (WDT). This full reset clears the crypto
peripheral state, allowing secure boot verification to succeed on the
next boot.
Risk with Aggressive Revocation
-------------------------------
If secure boot aggressive revocation is enabled (disabled by default in
IDF), this transient verification failure could mistakenly lead to
revocation of the secure boot digest.
If your product configuration has aggressive revocation enabled,
applying this fix is strongly recommended.
Frequency of Occurrence
-----------------------
The issue is rare and only occurs in corner cases involving
simultaneous use of the MPI peripheral and an immediate CPU reset.
Fix
---
This fix ensures that all crypto peripherals are explicitly reset prior
to any software-triggered restart (including panic scenarios),
guaranteeing a clean peripheral state for the next boot and preventing
incorrect secure boot behavior.
2025-04-15 19:06:26 +05:30
wuzhenghui
b3911c7c89
fix(esp_hw_support): fix unused OSC source deinit breaks XTAL32K configuration
2025-04-10 20:56:53 +08:00
Wu Zheng Hui
38fcc41ff2
Merge branch 'feat/enable_esp32p4_auto_clock_gate' into 'master'
...
feat(esp_hw_support): enable auto clock gating for multi peripherals
See merge request espressif/esp-idf!37986
2025-04-09 21:42:04 +08:00
wuzhenghui
6ca0614e89
feat(esp_hw_support): enable auto clock gating for multi peripherals
2025-04-09 17:07:49 +08:00
wuzhenghui
c84757d35e
fix(esp_hw_support): fix current leakage if ext32k slow clock source not exists
2025-04-08 20:07:47 +08:00
Chen Jichang
2cbc297969
refactor(gptimer): use group_id in clock ctrl functions
2025-04-08 10:20:48 +08:00
Chen Jichang
faacaaaf8f
feat(gptimer): support gptimer on esp32h4
2025-04-08 09:55:42 +08:00
Chen Jichang
44117b623d
refactor(esp_rom): remove specific chip name when including rom header
2025-03-17 18:53:26 +08:00
Li Shuai
350e3c3d06
fix(esp_system): update clk code for esp32h21
2025-03-17 11:24:39 +08:00
Li Shuai
8103ea67c7
change(esp_hw_support): pmu driver, hal and ll layer support for esp32h21
2025-03-17 11:24:39 +08:00
Chen Jichang
8e8c0573b4
feat(esp32h4): support esp_system, esp_timer and freertos (stage6)
2025-03-11 16:48:21 +08:00
