menu "ESP-Driver:I3C Master Configurations"

    config I3C_MASTER_ENABLED
        bool
        default y if SOC_I3C_MASTER_SUPPORTED && IDF_EXPERIMENTAL_FEATURES
        default n

    config I3C_MASTER_ISR_CACHE_SAFE
        bool "I3C ISR Cache-Safe"
        select I3C_MASTER_ISR_HANDLER_IN_IRAM
        select GDMA_ISR_HANDLER_IN_IRAM if SOC_GDMA_SUPPORTED
        default n
        help
            Ensure the I3C interrupt is Cache-Safe by allowing the interrupt handler to be
            executable when the cache is disabled (e.g. SPI Flash write).

    config I3C_MASTER_ENABLE_DEBUG_LOG
        bool "Enable I3C debug log"
        default n
        help
            whether to enable the debug log message for I3C driver.
            Note that this option only controls the I3C driver log, will not affect other drivers.

    config I3C_MASTER_ISR_HANDLER_IN_IRAM
        bool "Place I3C master ISR handler into IRAM"
        select GDMA_CTRL_FUNC_IN_IRAM if SOC_GDMA_SUPPORTED
        default n
        help
            Place I3C master ISR handler into IRAM for better performance and fewer cache misses.

endmenu # I3C Master Configurations