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247 lines
9.6 KiB
C
247 lines
9.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc_caps.h"
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#include "unity.h"
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#include "test_pms.h"
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#include "sdkconfig.h"
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/**
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* Test default access behavior for TEE mode
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*
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* Verifies the expected default access policy for TEE mode as defined by APM design.
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* Typically, masters in TEE mode should have full access to memory regions not explicitly
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* covered by an APM region entry.
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*
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* On ESP32-C6 and ESP32-H2, a known hardware bug causes TEE-mode masters to be denied access
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* to such regions, incorrectly triggering APM exceptions. This test validates that behavior.
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*
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* The test allocates a region in HP_MEM without an APM region entry and performs GDMA
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* read/write operations in TEE mode. It confirms:
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* - On affected SoCs (e.g., C6, H2): APM exceptions are expected.
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* - On unaffected SoCs: GDMA access should succeed without any APM violations.
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*/
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TEST_CASE("Test TEE mode default access", "[SYS_APM]")
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{
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test_tee_mode_default_access();
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}
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/**
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* Test HP-CPU access to CPU_PERI
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Configures multiple APM regions covering the CPU_PERI address space. For each region
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* and security mode (TEE, REE0, REE1, REE2), tests HP-CPU read/write access with varying
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* permissions: R-only (read passes, write fails) and W-only (write passes, read fail).
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* Verifies enforcement of APM access control by asserting expected APM violations.
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*/
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TEST_CASE("Test HP_CPU -> CPU_PERI access", "[SYS_APM]")
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{
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test_sys_apm_master_hp_cpu_slave_cpu_peri();
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}
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/**
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* Test HP-CPU access to HP_PERI
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*
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* Configures multiple APM regions covering the HP_PERI address space. For each region
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* and security mode (TEE, REE0, REE1, REE2), tests HP-CPU read/write access with varying
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* permissions: R-only (read passes, write fails) and W-only (write passes, read fail).
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* Verifies enforcement of APM access control by asserting expected APM violations.
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*/
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TEST_CASE("Test HP_CPU -> HP_PERI access", "[SYS_APM]")
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{
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test_sys_apm_master_hp_cpu_slave_hp_peri();
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}
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/**
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* Test HP-CPU access to LP_PERI
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Configures multiple APM regions covering the LP_PERI address space. For each region
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* and security mode (TEE, REE0, REE1, REE2), tests HP-CPU read/write access with varying
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* permissions: R-only (read passes, write fails) and W-only (write passes, read fail).
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* Verifies enforcement of APM access control by asserting expected APM violations.
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*/
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TEST_CASE("Test HP_CPU -> LP_PERI access", "[SYS_APM]")
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{
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test_sys_apm_master_hp_cpu_slave_lp_peri();
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}
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#if SOC_APM_CPU_APM_SUPPORTED
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/**
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* Test HP-CPU access to HP_MEM
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Divides a contiguous HP_MEM block into multiple APM regions and configures
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* their boundaries. For each region and security mode (TEE, REE0, REE1, REE2), tests
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* HP-CPU read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read and execute fail). Verifies enforcement of APM access control by
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* asserting expected APM violations.
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*/
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TEST_CASE("Test HP_CPU -> HP_MEM access", "[SYS_APM]")
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{
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test_sys_apm_master_hp_cpu_slave_hpmem();
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}
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#endif /* SOC_APM_CPU_APM_SUPPORTED */
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#if SOC_RTC_MEM_SUPPORTED
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/**
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* Test HP-CPU access to LP_MEM
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Divides a contiguous LP_MEM block into multiple APM regions and configures
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* their boundaries. For each region and security mode (TEE, REE0, REE1, REE2), tests
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* HP-CPU read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read and execute fail). Verifies enforcement of APM access control by
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* asserting expected APM violations.
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*/
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TEST_CASE("Test HP_CPU -> LP_MEM access", "[SYS_APM]")
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{
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test_sys_apm_master_hp_cpu_slave_lpmem();
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}
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#endif /* SOC_RTC_MEM_SUPPORTED */
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/**
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* Test GDMA access to HP_MEM
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Divides a contiguous HP_MEM block into multiple APM regions and configures
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* their boundaries. For each region and security mode (TEE, REE0, REE1, REE2), tests
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* GDMA read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read fails). Verifies enforcement of APM access control by
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* asserting expected APM violations.
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*/
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TEST_CASE("Test GDMA -> HP_MEM access", "[SYS_APM]")
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{
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test_sys_apm_master_gdma_slave_hpmem();
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}
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#if CONFIG_SPIRAM
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/**
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* Test GDMA access to EXT_MEM (SPIRAM)
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Divides a contiguous EXT_MEM block into multiple APM regions and configures
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* their boundaries. For each region and security mode (TEE, REE0, REE1, REE2), tests
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* GDMA read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read fails). Verifies enforcement of APM access control by
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* asserting expected APM violations.
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*/
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TEST_CASE("Test GDMA -> EXT_MEM access", "[SYS_APM]")
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{
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test_sys_apm_master_gdma_slave_extmem();
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}
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#endif /* CONFIG_SPIRAM */
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#if CONFIG_ULP_COPROC_ENABLED
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/**
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* Test LP-CPU access to LP_PERI
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Configures multiple APM regions covering the LP_PERI address space. For each region
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* and security mode (TEE, REE0, REE1, REE2), tests LP-CPU read/write access with varying
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* permissions: R-only (read passes, write fails) and W-only (write passes, read fail).
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* Verifies enforcement of APM access control by asserting expected APM violations.
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*/
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TEST_CASE("Test LP_CPU -> LP_PERI access", "[SYS_APM]")
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{
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test_sys_apm_master_lp_cpu_slave_lp_peri();
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}
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/**
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* Test LP-CPU access to LP_MEM
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Divides a contiguous LP_MEM block into multiple APM regions and configures
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* their boundaries. For each region and security mode (TEE, REE0, REE1, REE2), tests
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* LP-CPU read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read and execute fail). Verifies enforcement of APM access control by
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* asserting expected APM violations.
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*/
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TEST_CASE("Test LP_CPU -> LP_MEM access", "[SYS_APM]")
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{
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test_sys_apm_master_lp_cpu_slave_lpmem();
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}
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/**
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* Test LP-CPU access to HP_MEM
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*
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* SYS_APM uses region-based access control with start/end address boundaries and per-mode permissions.
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* Divides a contiguous HP_MEM block into multiple APM regions and configures
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* their boundaries. For each region and security mode (TEE, REE0, REE1, REE2), tests
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* LP-CPU read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read and execute fail). Verifies enforcement of APM access control by
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* asserting expected APM violations.
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*
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* Also verifies that LP-CPU can forcibly access HP_MEM regardless of APM permission settings.
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*/
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TEST_CASE("Test LP_CPU -> HP_MEM access", "[SYS_APM]")
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{
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test_sys_apm_master_lp_cpu_slave_hpmem();
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}
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#endif /* CONFIG_ULP_COPROC_ENABLED */
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#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
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/**
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* Test HP-CPU access to HP_PERI using PERI_APM
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*
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* PERI_APM uses per-peripheral based access control with per-mode permissions.
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* For each peripheral and security mode (TEE, REE0, REE1, REE2), tests HP-CPU
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* read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read fail). Verifies enforcement of access control
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* by asserting expected load/store access faults.
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*/
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TEST_CASE("Test HP_CPU -> HP_PERI access", "[PERI_APM]")
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{
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test_peri_apm_master_hp_cpu_slave_hp_peri();
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}
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/**
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* Test HP-CPU access to LP_PERI using PERI_APM
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*
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* PERI_APM uses per-peripheral based access control with per-mode permissions.
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* For each peripheral and security mode (TEE, REE0, REE1, REE2), tests HP-CPU
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* read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read fail). Verifies enforcement of access control
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* by asserting expected load/store access faults.
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*/
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TEST_CASE("Test HP_CPU -> LP_PERI access", "[PERI_APM]")
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{
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test_peri_apm_master_hp_cpu_slave_lp_peri();
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}
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#if CONFIG_ULP_COPROC_ENABLED
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/**
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* Test LP-CPU access to HP_PERI using PERI_APM
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*
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* PERI_APM uses per-peripheral based access control with per-mode permissions.
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* For each peripheral and security mode (TEE, REE0, REE1, REE2), tests LP-CPU
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* read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read fail). Verifies enforcement of access control
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* by asserting expected load/store access faults.
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*/
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TEST_CASE("Test LP_CPU -> HP_PERI access", "[PERI_APM]")
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{
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test_peri_apm_master_lp_cpu_slave_hp_peri();
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}
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/**
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* Test LP-CPU access to LP_PERI using PERI_APM
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*
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* PERI_APM uses per-peripheral based access control with per-mode permissions.
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* For each peripheral and security mode (TEE, REE0, REE1, REE2), tests LP-CPU
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* read/write access with varying permissions: R-only (read passes, write fails) and
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* W-only (write passes, read fail). Verifies enforcement of access control
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* by asserting expected load/store access faults.
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*/
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TEST_CASE("Test LP_CPU -> LP_PERI access", "[PERI_APM]")
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{
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test_peri_apm_master_lp_cpu_slave_lp_peri();
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}
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#endif /* CONFIG_ULP_COPROC_ENABLED */
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#endif /* SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL */
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