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https://github.com/espressif/esp-idf.git
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434 lines
14 KiB
C
434 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* Background
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*
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* This file is for the MSPI related, but not Flash driver related registers, these registers:
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* - may influence both Flash and PSRAM
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* - not related or directly related to Flash controller driver
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*
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* Some hints for naming convention:
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* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
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* - For others, the LL should start with `mspi_ll_`
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/pcr_struct.h"
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#include "soc/spi_mem_struct.h"
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#include "soc/spi_mem_reg.h"
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#include "hal/misc.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MSPI_TIMING_LL_MSPI_ID_0 0
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#define MSPI_TIMING_LL_MSPI_ID_1 1
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#define MSPI_LL_CORE_CLOCK_80_MHZ 80
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#define MSPI_LL_CORE_CLOCK_120_MHZ 120
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#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
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/************************** MSPI pll clock configurations **************************/
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/*
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* @brief Select FLASH clock source
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*
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* @param mspi_id mspi_id
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* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
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*/
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__attribute__((always_inline))
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static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
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{
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HAL_ASSERT(mspi_id == 0);
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switch (clk_src) {
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case FLASH_CLK_SRC_XTAL:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
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break;
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case FLASH_CLK_SRC_RC_FAST:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
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break;
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case FLASH_CLK_SRC_SPLL:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
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break;
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default:
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HAL_ASSERT(false);
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}
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}
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/**
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* @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
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*
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* @param mspi_id SPI0 / SPI1
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* @param core_clk_mhz core clock mhz
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*/
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static inline __attribute__((always_inline)) void mspi_timing_ll_set_core_clock(uint8_t mspi_id, uint32_t core_clk_mhz)
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{
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HAL_ASSERT(mspi_id == 0);
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uint32_t divider = 0;
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switch (core_clk_mhz) {
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case 80:
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divider = 6;
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break;
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case 120:
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divider = 4;
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break;
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default:
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HAL_ASSERT(false);
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
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}
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/**
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* @brief Enable the mspi core clock
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*
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* @param mspi_id SPI0 / SPI1
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* @param enable enable the core clock
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*/
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static inline __attribute__((always_inline)) void mspi_timing_ll_enable_core_clock(uint8_t mspi_id, bool enable)
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{
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PCR.mspi_conf.mspi_clk_en = enable;
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}
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/**
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* Reset the MSPI clock
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*/
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static inline __attribute__((always_inline)) void _mspi_timing_ll_reset_mspi(void)
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{
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PCR.mspi_clk_conf.mspi_axi_rst_en = 1;
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PCR.mspi_clk_conf.mspi_axi_rst_en = 0;
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// Wait for mspi to be ready
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while (!PCR.mspi_conf.mspi_ready) {
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;
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};
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}
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/**
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* Calculate spi_flash clock frequency division parameters for register.
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*
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* @param clkdiv frequency division factor
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*
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* @return Register setting for the given clock division factor.
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*/
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static inline uint32_t mspi_timing_ll_calculate_clock_reg(uint8_t clkdiv)
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{
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uint32_t div_parameter;
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// See comments of `clock` in `spi_mem_struct.h`
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if (clkdiv == 1) {
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div_parameter = (1 << 31);
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} else {
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div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
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}
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return div_parameter;
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}
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/**
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* Clear MSPI hw fifo
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*
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* @param mspi_id SPI0 / SPI1
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_clear_fifo(uint8_t mspi_id)
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{
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for (int i = 0; i < 16; i++) {
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REG_WRITE(SPI_MEM_W0_REG(mspi_id) + i * 4, 0);
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}
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}
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/*---------------------------------------------------------------
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FLASH
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---------------------------------------------------------------*/
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/**
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* @brief Set Flash clock
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*
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* @param mspi_id mspi_id
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* @param clock_conf Configuration value for flash clock
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_clock(uint32_t mspi_id, uint32_t clock_conf)
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{
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if (mspi_id == MSPI_TIMING_LL_MSPI_ID_0) {
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SPIMEM0.mem_clock.val = clock_conf;
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} else if (mspi_id == MSPI_TIMING_LL_MSPI_ID_1) {
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SPIMEM1.clock.val = clock_conf;
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}
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}
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/**
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* Enable Flash timing adjust clock
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*
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* @param mspi_id SPI0 / SPI1
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*/
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__attribute__((always_inline))
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static inline void mspi_timinng_ll_enable_flash_timing_adjust_clk(uint8_t mspi_id)
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{
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SPIMEM0.mem_timing_cali.mem_timing_clk_ena = true;
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}
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/**
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* Set MSPI Flash din mode
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*
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* @param mspi_id SPI0 / SPI1
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* @param din_mode Din mode value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_din_mode(uint8_t mspi_id, uint8_t din_mode)
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{
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uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(mspi_id)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
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| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
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| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
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REG_WRITE(SPI_MEM_DIN_MODE_REG(mspi_id), reg_val);
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
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}
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/**
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* Set MSPI Flash din num
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*
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* @param mspi_id SPI0 / SPI1
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* @param din_num Din num value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_din_num(uint8_t mspi_id, uint8_t din_num)
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{
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uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(mspi_id)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
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| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
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| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
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REG_WRITE(SPI_MEM_DIN_NUM_REG(mspi_id), reg_val);
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
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}
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/**
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* Set MSPI Flash extra dummy
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*
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* @param mspi_id SPI0 / SPI1
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* @param extra_dummy Extra dummy
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_extra_dummy(uint8_t mspi_id, uint8_t extra_dummy)
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{
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(mspi_id), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(mspi_id), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy, SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(mspi_id), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(mspi_id), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0, SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
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}
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/**
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* Get MSPI flash dummy info
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*
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* @param mspi_id SPI0 / SPI1
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* @param usr_dummy User dummy
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* @param extra_dummy Extra dummy
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_get_flash_dummy(uint8_t mspi_id, int *usr_dummy, int *extra_dummy)
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{
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*usr_dummy = REG_GET_FIELD(SPI_MEM_USER1_REG(mspi_id), SPI_MEM_USR_DUMMY_CYCLELEN);
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*extra_dummy = REG_GET_FIELD(SPI_MEM_TIMING_CALI_REG(mspi_id), SPI_MEM_EXTRA_DUMMY_CYCLELEN);
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}
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/**
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* Enable/Disable Flash variable dummy
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*
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* @param mspi_id SPI0 / SPI1
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* @param enable Enable / Disable
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_enable_flash_variable_dummy(uint8_t mspi_id, bool enable)
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{
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REG_SET_FIELD(SPI_MEM_DDR_REG(mspi_id), SPI_FMEM_VAR_DUMMY, enable);
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}
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/**
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* Get if cs setup is enabled or not
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*
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* @param mspi_id SPI0 / SPI1
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*
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* @return
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* true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool mspi_timing_ll_is_cs_setup_enabled(uint8_t mspi_id)
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{
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return REG_GET_BIT(SPI_MEM_USER_REG(mspi_id), SPI_MEM_CS_SETUP);
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}
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/**
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* Get cs setup val
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*
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* @param mspi_id SPI0 / SPI1
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*
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* @return
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* cs setup reg val
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*/
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static inline uint32_t mspi_timing_ll_get_cs_setup_val(uint8_t mspi_id)
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{
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return REG_GET_FIELD(SPI_MEM_CTRL2_REG(mspi_id), SPI_MEM_CS_SETUP_TIME);
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}
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/**
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* Get if cs hold is enabled or not
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*
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* @param mspi_id SPI0 / SPI1
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*
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* @return
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* true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool mspi_timing_ll_is_cs_hold_enabled(uint8_t mspi_id)
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{
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return REG_GET_FIELD(SPI_MEM_USER_REG(mspi_id), SPI_MEM_CS_HOLD);
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}
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/**
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* Get cs hold val
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*
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* @param mspi_id SPI0 / SPI1
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*
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* @return
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* cs hold reg val
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*/
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static inline uint32_t mspi_timing_ll_get_cs_hold_val(uint8_t mspi_id)
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{
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return REG_GET_FIELD(SPI_MEM_CTRL2_REG(mspi_id), SPI_MEM_CS_HOLD_TIME);
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}
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/**
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* Get clock reg val
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*
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* @param mspi_id SPI0 / SPI1
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*
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* @return
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* clock reg val
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*/
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__attribute__((always_inline))
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static inline uint32_t mspi_timing_ll_get_clock_reg(uint8_t mspi_id)
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{
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return READ_PERI_REG(SPI_MEM_CLOCK_REG(mspi_id));
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}
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/*---------------------------------------------------------------
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PSRAM
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---------------------------------------------------------------*/
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/**
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* @brief Set PSRAM clock
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*
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* @param mspi_id mspi_id
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* @param clock_conf Configuration value for psram clock
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_clock(uint32_t mspi_id, uint32_t clock_conf)
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{
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SPIMEM0.mem_sram_clk.val = clock_conf;
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}
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/**
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* @brief Set SPI1 bus clock to initialise PSRAM
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*
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* @param mspi_id mspi_id
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* @param clock_conf Configuration value for psram clock
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_spi1_bus_clock(uint32_t mspi_id, uint32_t clock_conf)
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{
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HAL_ASSERT(mspi_id == MSPI_TIMING_LL_MSPI_ID_1);
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SPIMEM1.clock.val = clock_conf;
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}
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/**
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* Enable PSRAM timing adjust clock
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*
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* @param mspi_id SPI0 / SPI1
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*/
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__attribute__((always_inline))
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static inline void mspi_timinng_ll_enable_psram_timing_adjust_clk(uint8_t mspi_id)
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{
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SPIMEM0.smem_timing_cali.smem_timing_clk_ena = true;
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}
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/**
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* Set MSPI PSRAM din mode
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*
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* @param mspi_id SPI0 / SPI1
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* @param din_mode Din mode value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_din_mode(uint8_t mspi_id, uint8_t din_mode)
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{
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uint32_t reg_val = (REG_READ(SPI_SMEM_DIN_MODE_REG(mspi_id)) & (~(SPI_SMEM_DIN0_MODE_M | SPI_SMEM_DIN1_MODE_M | SPI_SMEM_DIN2_MODE_M | SPI_SMEM_DIN3_MODE_M | SPI_SMEM_DIN4_MODE_M | SPI_SMEM_DIN5_MODE_M | SPI_SMEM_DIN6_MODE_M | SPI_SMEM_DIN7_MODE_M | SPI_SMEM_DINS_MODE_M)))
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| (din_mode << SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_SMEM_DIN3_MODE_S)
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| (din_mode << SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_SMEM_DINS_MODE_S);
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REG_WRITE(SPI_SMEM_DIN_MODE_REG(mspi_id), reg_val);
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
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}
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/**
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* Set MSPI PSRAM din num
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*
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* @param mspi_id SPI0 / SPI1
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* @param din_num Din num value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_din_num(uint8_t mspi_id, uint8_t din_num)
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{
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uint32_t reg_val = (REG_READ(SPI_SMEM_DIN_NUM_REG(mspi_id)) & (~(SPI_SMEM_DIN0_NUM_M | SPI_SMEM_DIN1_NUM_M | SPI_SMEM_DIN2_NUM_M | SPI_SMEM_DIN3_NUM_M | SPI_SMEM_DIN4_NUM_M | SPI_SMEM_DIN5_NUM_M | SPI_SMEM_DIN6_NUM_M | SPI_SMEM_DIN7_NUM_M | SPI_SMEM_DINS_NUM_M)))
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| (din_num << SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_SMEM_DIN3_NUM_S)
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| (din_num << SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_SMEM_DINS_NUM_S);
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REG_WRITE(SPI_SMEM_DIN_NUM_REG(mspi_id), reg_val);
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
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}
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/**
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* Set MSPI Octal PSRAM extra dummy
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*
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* @param mspi_id SPI0 / SPI1
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* @param extra_dummy Extra dummy
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_extra_dummy(uint8_t mspi_id, uint8_t extra_dummy)
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{
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
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} else {
|
|
CLEAR_PERI_REG_MASK(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_TIMING_CALI_M);
|
|
SET_PERI_REG_BITS(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
|
|
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
|
|
}
|
|
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
|
|
}
|
|
|
|
/**
|
|
* Get MSPI PSRAM dummy info
|
|
*
|
|
* @param mspi_id SPI0 / SPI1
|
|
* @param usr_rdummy User read dummy
|
|
* @param extra_dummy Extra dummy
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void mspi_timing_ll_get_psram_dummy(uint8_t mspi_id, int *usr_rdummy, int *extra_dummy)
|
|
{
|
|
*usr_rdummy = REG_GET_FIELD(SPI_MEM_CACHE_SCTRL_REG(mspi_id), SPI_MEM_SRAM_RDUMMY_CYCLELEN);
|
|
*extra_dummy = REG_GET_FIELD(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN);
|
|
}
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|