mirror of
https://github.com/espressif/esp-idf.git
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18091976ec
- Standardize all LL macros using atomic env variables with `do { ... } while (0)`
- Prevent potential macro misuse in control flow constructs (e.g., if/else)
- Affected targets: esp32, esp32c2, esp32c5, esp32s3, esp32p4, etc.
- Affected modules include: LCD, I2S, TIMER, and others
125 lines
3.5 KiB
C
125 lines
3.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for UHCI register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stdio.h>
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#include "hal/uhci_types.h"
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#include "soc/uhci_struct.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
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#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
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typedef enum {
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UHCI_RX_BREAK_CHR_EOF = 0x1,
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UHCI_RX_IDLE_EOF = 0x2,
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UHCI_RX_LEN_EOF = 0x4,
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UHCI_RX_EOF_MAX = 0x7,
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} uhci_rxeof_cfg_t;
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/**
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* @brief Enable the bus clock for UHCI module
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*
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* @param group_id Group ID
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* @param enable true to enable, false to disable
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*/
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static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
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{
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(void)group_id;
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HP_SYS_CLKRST.soc_clk_ctrl2.reg_uhci_apb_clk_en = enable;
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HP_SYS_CLKRST.soc_clk_ctrl1.reg_uhci_sys_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define uhci_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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_uhci_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset the UHCI module
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*
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* @param group_id Group ID
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*/
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static inline void _uhci_ll_reset_register(int group_id)
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{
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(void)group_id;
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uhci = 1;
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uhci = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define uhci_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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_uhci_ll_reset_register(__VA_ARGS__); \
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} while(0)
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static inline void uhci_ll_init(uhci_dev_t *hw)
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{
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typeof(hw->conf0) conf0_reg;
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hw->conf0.clk_en = 1;
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conf0_reg.val = 0;
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conf0_reg.clk_en = 1;
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hw->conf0.val = conf0_reg.val;
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hw->conf1.val = 0;
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}
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static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
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{
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hw->conf0.uart_sel = uart_num;
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}
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static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
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{
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if (seper_char->sub_chr_en) {
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hw->conf0.seper_en = 1;
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typeof(hw->esc_conf0) esc_conf0_reg;
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esc_conf0_reg.val = hw->esc_conf0.val;
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HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_char, seper_char->seper_chr);
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HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char0, seper_char->sub_chr1);
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HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char1, seper_char->sub_chr2);
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hw->esc_conf0.val = esc_conf0_reg.val;
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hw->escape_conf.tx_c0_esc_en = 1;
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hw->escape_conf.rx_c0_esc_en = 1;
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} else {
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hw->conf0.seper_en = 0;
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hw->escape_conf.val = 0;
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}
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}
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static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
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{
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if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
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hw->conf0.uart_rx_brk_eof_en = 1;
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}
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if (eof_mode & UHCI_RX_IDLE_EOF) {
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hw->conf0.uart_idle_eof_en = 1;
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}
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if (eof_mode & UHCI_RX_LEN_EOF) {
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hw->conf0.len_eof_en = 1;
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}
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}
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static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
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{
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hw->pkt_thres.pkt_thrs = length;
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}
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#ifdef __cplusplus
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}
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#endif
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