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05e09a5bacb231f3699815801feff035a0e26a0a
esp-idf/components/soc/esp32
History
Angus Gratton 05e09a5bac ci: Only run XTAL unit tests assuming board has an XTAL, run less repeats
2018-05-15 15:43:24 +08:00
..
include/soc
rename clock enable and reset bits for SPI modules
2018-05-14 16:45:03 +08:00
test
ci: Only run XTAL unit tests assuming board has an XTAL, run less repeats
2018-05-15 15:43:24 +08:00
cpu_util.c
esp_restart: fix possible race while stalling other CPU, enable WDT early
2017-10-26 19:53:53 +08:00
i2c_apll.h
soc: add source code of rtc_clk, rtc_pm
2017-04-11 15:45:54 +08:00
i2c_bbpll.h
soc: add source code of rtc_clk, rtc_pm
2017-04-11 15:45:54 +08:00
i2c_rtc_clk.h
soc: add source code of rtc_clk, rtc_pm
2017-04-11 15:45:54 +08:00
rtc_clk.c
soc/rtc: fix switching between 80/160 and 240MHz
2018-03-27 10:55:59 +08:00
rtc_init.c
soc/rtc: restore dbg attenuation when waking from sleep
2018-04-26 18:52:46 +08:00
rtc_pm.c
soc/rtc: don’t switch frequency in rtc_sleep_init
2018-04-26 18:52:45 +08:00
rtc_sleep.c
sleep: optimize light sleep wakeup latency
2018-04-26 19:36:47 +08:00
rtc_time.c
soc/rtc: add a function to wait for slow clock cycle
2017-10-26 19:53:53 +08:00
soc_log.h
soc: add source code of rtc_clk, rtc_pm
2017-04-11 15:45:54 +08:00
soc_memory_layout.c
Add logic to make external RAM usable with malloc()
2017-09-28 17:17:50 +08:00
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