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139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-C5 LP_AON register operations
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#pragma once
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "soc/lp_aon_struct.h"
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#include "hal/misc.h"
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#include "esp32c5/rom/rtc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Get ext1 wakeup source status
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* @return The lower 8 bits of the returned value are the bitmap of
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* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
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*/
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static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
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}
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/**
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* @brief Clear the ext1 wakeup source status
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*/
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static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
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}
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/**
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* @brief Set the wake-up LP_IO of the ext1 wake-up source
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* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
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* @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level
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* each bit's corresponding position is set to 0, the wakeup level will be low
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* on the contrary, each bit's corresponding position is set to 1, the wakeup
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* level will be high
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*/
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static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask);
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask);
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}
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/**
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* @brief Clear all ext1 wakup-source setting
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*/
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static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
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}
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/**
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* @brief Get ext1 wakeup source setting
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* @return The lower 8 bits of the returned value are the bitmap of
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* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
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*/
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static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
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}
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/**
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* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
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* Set the flag to inform
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* @param true: deepsleep false: lightsleep
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*/
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static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
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{
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if (dslp) {
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REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
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} else {
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REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
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}
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}
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/**
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* @brief Set the maximum number of linked lists supported by REGDMA
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* @param count: the maximum number of regdma link
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*/
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static inline void lp_aon_ll_set_regdma_link_count(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, branch_link_length_aon, count);
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}
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/**
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* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
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* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
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* @param count: the maximum number of loop
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*/
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static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_work_tout_thres_aon, count);
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}
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/**
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* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
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* registers and gets stuck on the bus, a timeout will be triggered.
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* @param count: the maximum number of time
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*/
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static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_backup_tout_thres_aon, count);
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}
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/**
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* @brief Set the regdma_link_addr
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* @param addr: the addr of regdma_link
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*/
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static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr);
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}
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static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count);
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}
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static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval);
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}
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#ifdef __cplusplus
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}
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#endif
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