mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-03 14:01:53 +00:00
375 lines
10 KiB
Plaintext
375 lines
10 KiB
Plaintext
/* Default entry point: */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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/* RTC fast memory holds RTC wake stub code,
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including from any source file named rtc_wake_stub*.c
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*/
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.rtc.text :
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{
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_rtc_text_start = ABSOLUTE(.);
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. = ALIGN(4);
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_rtc_code_start = .;
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mapping[rtc_text]
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*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
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_rtc_code_end = .;
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/* possibly align + add 16B for CPU dummy speculative instr. fetch */
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. = ((_rtc_code_end - _rtc_code_start) == 0) ? ALIGN(0) : ALIGN(4) + 16;
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_rtc_text_end = ABSOLUTE(.);
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} > rtc_iram_seg
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/*
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This section is required to skip rtc.text area because rtc_iram_seg and
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rtc_data_seg are reflect the same address space on different buses.
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*/
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.rtc.dummy :
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{
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_rtc_dummy_start = ABSOLUTE(.);
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_rtc_fast_start = ABSOLUTE(.);
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. = SIZEOF(.rtc.text);
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_rtc_dummy_end = ABSOLUTE(.);
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} > rtc_data_seg
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/* This section located in RTC FAST Memory area.
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It holds data marked with RTC_FAST_ATTR attribute.
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See the file "esp_attr.h" for more information.
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*/
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.rtc.force_fast :
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{
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. = ALIGN(4);
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_rtc_force_fast_start = ABSOLUTE(.);
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_coredump_rtc_fast_start = ABSOLUTE(.);
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mapping[rtc_fast_coredump]
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_coredump_rtc_fast_end = ABSOLUTE(.);
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*(.rtc.force_fast .rtc.force_fast.*)
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. = ALIGN(4) ;
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_rtc_force_fast_end = ABSOLUTE(.);
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} > rtc_data_seg
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/* RTC data section holds RTC wake stub
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data/rodata, including from any source file
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named rtc_wake_stub*.c and the data marked with
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RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
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The memory location of the data is dependent on
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CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM option.
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*/
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.rtc.data :
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{
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_rtc_data_start = ABSOLUTE(.);
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/* coredump mapping */
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_coredump_rtc_start = ABSOLUTE(.);
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mapping[rtc_coredump]
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_coredump_rtc_end = ABSOLUTE(.);
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/* should be placed after coredump mapping */
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mapping[rtc_data]
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*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)
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_rtc_data_end = ABSOLUTE(.);
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} > rtc_data_location
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/* RTC bss, from any source file named rtc_wake_stub*.c */
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.rtc.bss (NOLOAD) :
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{
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_rtc_bss_start = ABSOLUTE(.);
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*rtc_wake_stub*.*(.bss .bss.*)
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*rtc_wake_stub*.*(COMMON)
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mapping[rtc_bss]
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_rtc_bss_end = ABSOLUTE(.);
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} > rtc_data_location
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/* This section holds data that should not be initialized at power up
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and will be retained during deep sleep.
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User data marked with RTC_NOINIT_ATTR will be placed
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into this section. See the file "esp_attr.h" for more information.
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The memory location of the data is dependent on
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CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM option.
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*/
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.rtc_noinit (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_noinit_start = ABSOLUTE(.);
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*(.rtc_noinit .rtc_noinit.*)
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. = ALIGN(4) ;
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_rtc_noinit_end = ABSOLUTE(.);
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} > rtc_data_location
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/* This section located in RTC SLOW Memory area.
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It holds data marked with RTC_SLOW_ATTR attribute.
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See the file "esp_attr.h" for more information.
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*/
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.rtc.force_slow :
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{
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. = ALIGN(4);
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_rtc_force_slow_start = ABSOLUTE(.);
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*(.rtc.force_slow .rtc.force_slow.*)
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. = ALIGN(4) ;
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_rtc_force_slow_end = ABSOLUTE(.);
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} > rtc_slow_seg
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/* Get size of rtc slow data based on rtc_data_location alias */
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_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_slow_end - _rtc_data_start)
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: (_rtc_force_slow_end - _rtc_force_slow_start);
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_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_fast_end - _rtc_fast_start)
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: (_rtc_noinit_end - _rtc_fast_start);
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ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
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"RTC_SLOW segment data does not fit.")
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ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
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"RTC_FAST segment data does not fit.")
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/* Send .iram0 code to iram */
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.iram0.vectors :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to IRAM */
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_vector_table = ABSOLUTE(.);
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/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
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. = 0x0;
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KEEP(*(.WindowVectors.text));
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. = 0x180;
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KEEP(*(.Level2InterruptVector.text));
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. = 0x1c0;
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KEEP(*(.Level3InterruptVector.text));
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. = 0x200;
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KEEP(*(.Level4InterruptVector.text));
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. = 0x240;
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KEEP(*(.Level5InterruptVector.text));
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. = 0x280;
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KEEP(*(.DebugExceptionVector.text));
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. = 0x2c0;
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KEEP(*(.NMIExceptionVector.text));
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. = 0x300;
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KEEP(*(.KernelExceptionVector.text));
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. = 0x340;
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KEEP(*(.UserExceptionVector.text));
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. = 0x3C0;
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KEEP(*(.DoubleExceptionVector.text));
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. = 0x400;
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_invalid_pc_placeholder = ABSOLUTE(.);
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*(.*Vector.literal)
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*(.UserEnter.literal);
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*(.UserEnter.text);
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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_init_end = ABSOLUTE(.);
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} > iram0_0_seg
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.iram0.text :
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{
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/* Code marked as runnning out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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mapping[iram0_text]
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/* added to maintain compability */
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_coredump_iram_start = 0;
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_coredump_iram_end = 0;
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/* align + add 16B for CPU dummy speculative instr. fetch */
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. = ALIGN(4) + 16;
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_iram_text_end = ABSOLUTE(.);
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_iram_end = ABSOLUTE(.);
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} > iram0_0_seg
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.dram0_reserved_for_iram (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} > dram0_0_seg
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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/* coredump mapping */
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_coredump_dram_start = ABSOLUTE(.);
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mapping[dram_coredump]
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_coredump_dram_end = ABSOLUTE(.);
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/* should be placed after coredump mapping */
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_esp_system_init_fn_array_start = ABSOLUTE(.);
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KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*)))
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_esp_system_init_fn_array_end = ABSOLUTE(.);
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mapping[dram0_data]
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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} > dram0_0_seg
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/*This section holds data that should not be initialized at power up.
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The section located in Internal SRAM memory region. The macro _NOINIT
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can be used as attribute to place data into this section.
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See the esp_attr.h file for more information.
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*/
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.noinit (NOLOAD):
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{
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. = ALIGN(4);
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_noinit_start = ABSOLUTE(.);
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*(.noinit .noinit.*)
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. = ALIGN(4) ;
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_noinit_end = ABSOLUTE(.);
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} > dram0_0_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.ext_ram.bss*)
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mapping[dram0_bss]
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} > dram0_0_seg
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/* When modifying the alignment, update tls_section_alignment in pxPortInitialiseStack */
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.flash.rodata : ALIGN(0x10)
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{
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_rodata_reserved_start = ABSOLUTE(.);
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_rodata_start = ABSOLUTE(.);
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*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
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*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
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mapping[flash_rodata]
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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. = (. + 3) & ~ 3;
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__eh_frame = ABSOLUTE(.);
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KEEP(*(.eh_frame))
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. = (. + 7) & ~ 3;
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/* C++ constructor and destructor tables
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Make a point of not including anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt
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*/
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__init_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.*(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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/* Addresses of memory regions reserved via
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SOC_RESERVE_MEMORY_REGION() */
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soc_reserved_memory_region_start = ABSOLUTE(.);
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KEEP (*(.reserved_memory_address))
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soc_reserved_memory_region_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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_thread_local_start = ABSOLUTE(.);
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*(.tdata)
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*(.tdata.*)
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*(.tbss)
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*(.tbss.*)
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_thread_local_end = ABSOLUTE(.);
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_rodata_reserved_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >default_rodata_seg
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.flash.text :
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{
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_stext = .;
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_instruction_reserved_start = ABSOLUTE(.);
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_text_start = ABSOLUTE(.);
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mapping[flash_text]
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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/* Similar to _iram_start, this symbol goes here so it is
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resolved by addr2line in preference to the first symbol in
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the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} >default_code_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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. = ALIGN (4);
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_iram_end = ABSOLUTE(.);
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} > iram0_0_seg
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/* Marks the end of data, bss and possibly rodata */
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.dram0.heap_start (NOLOAD) :
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{
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. = ALIGN (8);
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_heap_start = ABSOLUTE(.);
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} > dram0_0_seg
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}
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ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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"IRAM0 segment data does not fit.")
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ASSERT(((_heap_start - _data_start) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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