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45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/interrupt_matrix_reg.h"
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#include "soc/plic_reg.h"
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#include "soc/soc_caps.h"
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#ifdef __has_include
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# if __has_include("sdkconfig.h")
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# include "sdkconfig.h"
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# endif
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#endif
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#if CONFIG_SECURE_ENABLE_TEE
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#define INTERRUPT_PRIO_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
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#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_UXINT_THRESH_REG
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#else
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#define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
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#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG
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#endif
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/**
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* ESP32H2 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
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* Keep the following macros for backward compatibility reasons
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*/
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#if CONFIG_SECURE_ENABLE_TEE
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#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_UXINT_ENABLE_REG
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#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_UXINT_THRESH_REG
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#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_UXINT_CLEAR_REG
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#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_UXINT_TYPE_REG
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#define INTC_INT_PRIO_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
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#else
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#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
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#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
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#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG
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#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
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#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
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#endif
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#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE
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