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https://github.com/espressif/esp-idf.git
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347 lines
17 KiB
C
347 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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************************* ESP32H4 Root Clock Source ****************************
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* 1) Internal 20MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
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*
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* This RC oscillator generates a ~20MHz clock signal output as the RC_FAST_CLK.
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*
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
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*
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* 2) External 32MHz Crystal Clock: XTAL
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*
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* 3) Internal 600kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
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*
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* This RC oscillator generates a ~600kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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*
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* 4) External 32kHz Crystal Clock (optional): XTAL32K
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*
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* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
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* pins.
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*
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* XTAL32K_CLK can also be calibrated to get its exact frequency.
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*
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* 5) External Slow Clock (optional): OSC_SLOW
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*
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* A slow clock signal generated by an external circuit can be connected to GPIO5 to be the clock source for the
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* RTC_SLOW_CLK.
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*
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* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
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*/
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/* The pin number to connect the external slow clock (OSC_SLOW_CLK), XTAL_32K_P */
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#define SOC_EXT_OSC_SLOW_GPIO_NUM 5
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/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 20 MHz +/- 7% */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 20000000 /*!< Approximate RC_FAST_CLK frequency in Hz */
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 600000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
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#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
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#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
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// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
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// {loc}: EXT, INT
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// {type}: XTAL, RC
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// [attr] - optional: [frequency], FAST, SLOW
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/**
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* @brief Root clock
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*/
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typedef enum {
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 20MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 600kHz RC oscillator */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
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SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin5 */
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} soc_root_clk_t;
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/**
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* @brief ROOT clock circuit, which requires explicitly enabling the targeting circuit to use
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*/
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typedef enum {
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SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the PLL generator circuit */
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// SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
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} soc_root_clk_circuit_t;
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/**
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* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */
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// SOC_CPU_CLK_SRC_XTAL_X2 = 2, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
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SOC_CPU_CLK_SRC_PLL = 3, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
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SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
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} soc_cpu_clk_src_t;
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/**
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* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4 = 0, /*!< Select RC_SLOW_D4_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_DEFAULT = SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4, /*!< RC_SLOW_D4_CLK is the default clock source for RTC_SLOW_CLK */
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} soc_rtc_slow_clk_src_t;
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/**
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* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
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} soc_rtc_fast_clk_src_t;
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/**
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* @brief Possible main XTAL frequency options on the target
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* @note Enum values equal to the frequency value in MHz
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* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
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* the supported ones.
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*/
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typedef enum {
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SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
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} soc_xtal_freq_t;
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// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
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// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
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// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
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/**
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* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
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*
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* @note enum starts from 1, to save 0 for special purpose
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*/
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typedef enum {
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// For CPU domain
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SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or XTAL_X2 by configuring soc_cpu_clk_src_t */
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// For RTC domain
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SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW_D4, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, BLE
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// SOC_MOD_CLK_XTAL_X2_F32M, /*!< XTAL_X2_F32M_CLK is derived from XTAL_X2 (clock gating + fixed divider of 2), it has a fixed frequency of 32MHz */
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SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
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// SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
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SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
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SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
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SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 32MHz crystal */
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SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
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} soc_module_clk_t;
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//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
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/**
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* @brief Type of SYSTIMER clock source
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*/
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typedef enum {
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SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
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SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
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SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
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} soc_periph_systimer_clk_src_t;
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//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of GPTimer
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*
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* The following code can be used to iterate all possible clocks:
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* @code{c}
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* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
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* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
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* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
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* // Test GPTimer with the clock `clk`
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* }
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* @endcode
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*/
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#if SOC_CLK_TREE_SUPPORTED
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#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
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#else
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#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
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#endif
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/**
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* @brief Type of GPTimer clock source
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*/
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typedef enum {
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GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
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GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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#if SOC_CLK_TREE_SUPPORTED
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GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */
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#else
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GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice if no clk_tree */
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#endif
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} soc_periph_gptimer_clk_src_t;
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/**
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* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
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*/
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typedef enum {
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TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */
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TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
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TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */
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} soc_periph_tg_clk_src_legacy_t;
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//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of RMT
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*/
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#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief Type of RMT clock source
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*/
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typedef enum {
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RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
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} soc_periph_rmt_clk_src_t;
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/**
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* @brief Type of RMT clock source, reserved for the legacy RMT driver
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*/
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typedef enum {
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RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
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RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
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} soc_periph_rmt_clk_src_legacy_t;
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///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
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/**
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* @brief Type of UART clock source, reserved for the legacy UART driver
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*/
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typedef enum {
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UART_SCLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock is PLL_F48M */
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UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
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UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
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UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */
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} soc_periph_uart_clk_src_legacy_t;
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/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of SPI
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*/
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#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief Type of SPI clock source.
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*/
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typedef enum {
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SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
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SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
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SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
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SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
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} soc_periph_spi_clk_src_t;
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//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of MWDT
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*/
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#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief MWDT clock source
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*/
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typedef enum {
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MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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MWDT_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL fixed 48MHz as the source clock */
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MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
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MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
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} soc_periph_mwdt_clk_src_t;
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//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of FLASH MSPI controller
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*/
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#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief FLASH MSPI controller clock source
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*/
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typedef enum {
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FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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// FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
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FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
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FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
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FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
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} soc_periph_flash_clk_src_t;
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////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
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/**
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* @brief Clock frequency calibration source selection
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*/
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typedef enum {
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CLK_CAL_RC_SLOW = 0, /*!< Select to calibrate RC_SLOW_CLK */
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CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
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CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
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CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
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CLK_CAL_CPU, /*!< Select to calibrate CPU_CLK */
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CLK_CAL_AHB, /*!< Select to calibrate AHB_CLK */
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CLK_CAL_APB, /*!< Select to calibrate APB_CLK */
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CLK_CAL_SEC, /*!< Select to calibrate SEC_CLK */
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CLK_CAL_MSPI, /*!< Select to calibrate MSPI_CLK */
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CLK_CAL_IOMUX, /*!< Select to calibrate IOMUX_CLK */
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CLK_CAL_PARLIO_RX, /*!< Select to calibrate PARLIO_RX_CLK */
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CLK_CAL_PARLIO_TX, /*!< Select to calibrate PARLIO_TX_CLK */
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CLK_CAL_GPSPI3_MST, /*!< Select to calibrate GPSPI3_MST_CLK */
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CLK_CAL_GPSPI2_MST, /*!< Select to calibrate GPSPI2_MST_CLK */
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CLK_CAL_EXT_IO, /*!< Select to calibrate an external clock from an IO */
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} soc_timg0_calibration_clk_src_t;
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/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2C
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*/
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#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief Type of I2C clock source.
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*/
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typedef enum {
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I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
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} soc_periph_i2c_clk_src_t;
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///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2S
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*/
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#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
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/**
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* @brief I2S clock source enum
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*/
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
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I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
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// I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
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} soc_periph_i2s_clk_src_t;
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#ifdef __cplusplus
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}
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#endif
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