mirror of
https://github.com/espressif/esp-idf.git
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ce388a4111
Refactored internal EMAC DMA access. Added MPLL acquire to manage access to the MPLL by multiple periphs.
248 lines
11 KiB
C
248 lines
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "hal/emac_hal.h"
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#include "hal/emac_ll.h"
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static esp_err_t emac_hal_flush_trans_fifo(emac_hal_context_t *hal)
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{
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emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
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/* no other writes to the Operation Mode register until the flush tx fifo bit is cleared */
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for (uint32_t i = 0; i < 1000; i++) {
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if (emac_ll_get_flush_trans_fifo(hal->dma_regs) == 0) {
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return ESP_OK;
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}
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}
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return ESP_ERR_TIMEOUT;
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}
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void emac_hal_init(emac_hal_context_t *hal)
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{
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hal->dma_regs = &EMAC_DMA;
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hal->mac_regs = &EMAC_MAC;
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#if CONFIG_IDF_TARGET_ESP32
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hal->ext_regs = &EMAC_EXT;
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#endif
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}
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void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
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{
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/* Tell MAC system clock Frequency in MHz, which will determine the frequency range of MDC(1MHz~2.5MHz) */
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if (freq >= 20000000 && freq < 35000000) {
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emac_ll_set_csr_clock_division(hal->mac_regs, 2); // CSR clock/16
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} else if (freq >= 35000000 && freq < 60000000) {
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emac_ll_set_csr_clock_division(hal->mac_regs, 3); // CSR clock/26
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} else if (freq >= 60000000 && freq < 100000000) {
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emac_ll_set_csr_clock_division(hal->mac_regs, 0); // CSR clock/42
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} else if (freq >= 100000000 && freq < 150000000) {
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emac_ll_set_csr_clock_division(hal->mac_regs, 1); // CSR clock/62
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} else if (freq >= 150000000 && freq < 250000000) {
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emac_ll_set_csr_clock_division(hal->mac_regs, 4); // CSR clock/102
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} else {
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emac_ll_set_csr_clock_division(hal->mac_regs, 5); // CSR clock/124
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}
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}
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void emac_hal_set_rx_tx_desc_addr(emac_hal_context_t *hal, eth_dma_rx_descriptor_t *rx_desc, eth_dma_tx_descriptor_t *tx_desc)
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{
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emac_ll_set_rx_desc_addr(hal->dma_regs, (uint32_t)rx_desc);
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emac_ll_set_tx_desc_addr(hal->dma_regs, (uint32_t)tx_desc);
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}
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void emac_hal_init_mac_default(emac_hal_context_t *hal)
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{
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/* MACCR Configuration */
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/* Enable the watchdog on the receiver, frame longer than 2048 Bytes is not allowed */
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emac_ll_watchdog_enable(hal->mac_regs, true);
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/* Enable the jabber timer on the transmitter, frame longer than 2048 Bytes is not allowed */
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emac_ll_jabber_enable(hal->mac_regs, true);
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/* minimum IFG between frames during transmission is 96 bit times */
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emac_ll_set_inter_frame_gap(hal->mac_regs, EMAC_LL_INTERFRAME_GAP_96BIT);
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/* Enable Carrier Sense During Transmission */
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emac_ll_carrier_sense_enable(hal->mac_regs, true);
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/* Select speed: port: 10/100 Mbps, here set default 100M, afterwards, will reset by auto-negotiation */
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emac_ll_set_port_speed(hal->mac_regs, ETH_SPEED_100M);
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/* Allow the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
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emac_ll_recv_own_enable(hal->mac_regs, true);
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/* Disable internal loopback mode */
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emac_ll_loopback_enable(hal->mac_regs, false);
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/* Select duplex mode: here set default full duplex, afterwards, will reset by auto-negotiation */
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emac_ll_set_duplex(hal->mac_regs, ETH_DUPLEX_FULL);
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/* Select the checksum mode for received frame payload's TCP/UDP/ICMP headers */
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emac_ll_checksum_offload_mode(hal->mac_regs, ETH_CHECKSUM_HW);
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/* Enable MAC retry transmission when a colision occurs in half duplex mode */
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emac_ll_retry_enable(hal->mac_regs, true);
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/* MAC passes all incoming frames to host, without modifying them */
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emac_ll_auto_pad_crc_strip_enable(hal->mac_regs, false);
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/* Set Back-Off limit time before retry a transmittion after a collision */
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emac_ll_set_back_off_limit(hal->mac_regs, EMAC_LL_BACKOFF_LIMIT_10);
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/* Disable deferral check, MAC defers until the CRS signal goes inactive */
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emac_ll_deferral_check_enable(hal->mac_regs, false);
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/* Set preamble length 7 Bytes */
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emac_ll_set_preamble_length(hal->mac_regs, EMAC_LL_PREAMBLE_LENGTH_7);
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/* MACFFR Configuration */
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/* Receiver module passes only those frames to the Application that pass the SA or DA address filter */
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emac_ll_receive_all_enable(hal->mac_regs, false);
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/* Disable source address filter */
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emac_ll_set_src_addr_filter(hal->mac_regs, EMAC_LL_SOURCE_ADDR_FILTER_DISABLE);
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emac_ll_sa_inverse_filter_enable(hal->mac_regs, false);
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/* MAC blocks all control frames */
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emac_ll_set_pass_ctrl_frame_mode(hal->mac_regs, EMAC_LL_CONTROL_FRAME_BLOCKALL);
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/* AFM module passes all received broadcast frames and multicast frames */
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emac_ll_broadcast_frame_enable(hal->mac_regs, true);
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emac_ll_pass_all_multicast_enable(hal->mac_regs, true);
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/* Address Check block operates in normal filtering mode for the DA address */
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emac_ll_da_inverse_filter_enable(hal->mac_regs, false);
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/* Disable Promiscuous Mode */
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emac_ll_promiscuous_mode_enable(hal->mac_regs, false);
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}
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void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable)
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{
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/* MACFCR Configuration */
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if (enable) {
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/* Pause time */
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emac_ll_set_pause_time(hal->mac_regs, EMAC_LL_PAUSE_TIME);
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/* Enable generation of Zero-Quanta Pause Control frames */
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emac_ll_zero_quanta_pause_enable(hal->mac_regs, true);
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/* Threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
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emac_ll_set_pause_low_threshold(hal->mac_regs, EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_28);
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/* Don't allow MAC detect Pause frames with MAC address0 unicast address and unique multicast address */
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emac_ll_unicast_pause_frame_detect_enable(hal->mac_regs, false);
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/* Enable MAC to decode the received Pause frame and disable its transmitter for a specific time */
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emac_ll_receive_flow_ctrl_enable(hal->mac_regs, true);
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/* Enable MAC to transmit Pause frames in full duplex mode or the MAC back-pressure operation in half duplex mode */
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emac_ll_transmit_flow_ctrl_enable(hal->mac_regs, true);
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} else {
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emac_ll_clear(hal->mac_regs);
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}
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}
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void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *hal_config)
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{
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/* DMAOMR Configuration */
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/* Enable Dropping of TCP/IP Checksum Error Frames */
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emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true);
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#if CONFIG_IDF_TARGET_ESP32P4
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/* Disable Receive Store Forward (Rx FIFO is only 256B) */
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emac_ll_recv_store_forward_enable(hal->dma_regs, false);
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#else
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/* Enable Receive Store Forward */
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emac_ll_recv_store_forward_enable(hal->dma_regs, true);
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#endif
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/* Enable Flushing of Received Frames because of the unavailability of receive descriptors or buffers */
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emac_ll_flush_recv_frame_enable(hal->dma_regs, true);
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/* Disable Transmit Store Forward */
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emac_ll_trans_store_forward_enable(hal->dma_regs, false);
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/* Flush Transmit FIFO */
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emac_hal_flush_trans_fifo(hal);
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/* Transmit Threshold Control */
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emac_ll_set_transmit_threshold(hal->dma_regs, EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_64);
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/* Disable Forward Error Frame */
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emac_ll_forward_err_frame_enable(hal->dma_regs, false);
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/* Disable forward undersized good frame */
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emac_ll_forward_undersized_good_frame_enable(hal->dma_regs, false);
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/* Receive Threshold Control */
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emac_ll_set_recv_threshold(hal->dma_regs, EMAC_LL_RECEIVE_THRESHOLD_CONTROL_64);
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/* Allow the DMA to process a second frame of Transmit data even before obtaining the status for the first frame */
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emac_ll_opt_second_frame_enable(hal->dma_regs, true);
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/* DMABMR Configuration */
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/* Enable Mixed Burst */
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emac_ll_mixed_burst_enable(hal->dma_regs, true);
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/* Enable Address Aligned Beates */
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emac_ll_addr_align_enable(hal->dma_regs, true);
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/* Don't use Separate PBL */
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emac_ll_use_separate_pbl_enable(hal->dma_regs, false);
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/* Set Rx/Tx DMA Burst Length */
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emac_ll_set_prog_burst_len(hal->dma_regs, hal_config->dma_burst_len);
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/* Enable Enhanced Descriptor,8 Words(32 Bytes) */
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emac_ll_enhance_desc_enable(hal->dma_regs, true);
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/* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
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emac_ll_set_desc_skip_len(hal->dma_regs, 0);
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/* DMA Arbitration Scheme */
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emac_ll_fixed_arbitration_enable(hal->dma_regs, false);
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/* Set priority ratio in the weighted round-robin arbitration between Rx DMA and Tx DMA */
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emac_ll_set_priority_ratio(hal->dma_regs, EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1);
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}
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void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write)
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{
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/* Write the result value into the MII Address register */
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emac_ll_set_phy_addr(hal->mac_regs, phy_addr);
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/* Set the PHY register address */
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emac_ll_set_phy_reg(hal->mac_regs, phy_reg);
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/* Set as write mode */
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emac_ll_write_enable(hal->mac_regs, write);
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/* Set MII busy bit */
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emac_ll_set_busy(hal->mac_regs, true);
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}
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void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr)
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{
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/* Make sure mac address is unicast type */
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if (!(mac_addr[0] & 0x01)) {
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emac_ll_set_addr(hal->mac_regs, mac_addr);
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}
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}
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void emac_hal_start(emac_hal_context_t *hal)
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{
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/* Enable Ethernet MAC and DMA Interrupt */
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emac_ll_enable_corresponding_intr(hal->dma_regs, EMAC_LL_CONFIG_ENABLE_INTR_MASK);
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/* Clear all pending interrupts */
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emac_ll_clear_all_pending_intr(hal->dma_regs);
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/* Enable transmit state machine of the MAC for transmission on the MII */
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emac_ll_transmit_enable(hal->mac_regs, true);
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/* Start DMA transmission */
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/* Note that the EMAC Databook states the DMA could be started prior enabling
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the MAC transmitter. However, it turned out that such order may cause the MAC
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transmitter hangs */
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emac_ll_start_stop_dma_transmit(hal->dma_regs, true);
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/* Start DMA reception */
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emac_ll_start_stop_dma_receive(hal->dma_regs, true);
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/* Enable receive state machine of the MAC for reception from the MII */
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emac_ll_receive_enable(hal->mac_regs, true);
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}
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esp_err_t emac_hal_stop(emac_hal_context_t *hal)
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{
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/* Stop DMA transmission */
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emac_ll_start_stop_dma_transmit(hal->dma_regs, false);
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if (emac_ll_transmit_frame_ctrl_status(hal->mac_regs) != 0x0) {
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/* Previous transmit in progress */
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return ESP_ERR_INVALID_STATE;
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}
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/* Disable transmit state machine of the MAC for transmission on the MII */
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emac_ll_receive_enable(hal->mac_regs, false);
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/* Disable receive state machine of the MAC for reception from the MII */
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emac_ll_transmit_enable(hal->mac_regs, false);
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if (emac_ll_receive_read_ctrl_state(hal->mac_regs) != 0x0) {
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/* Previous receive copy in progress */
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return ESP_ERR_INVALID_STATE;
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}
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/* Stop DMA reception */
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emac_ll_start_stop_dma_receive(hal->dma_regs, false);
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/* Flush Transmit FIFO */
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emac_hal_flush_trans_fifo(hal);
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/* Disable Ethernet MAC and DMA Interrupt */
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emac_ll_disable_all_intr(hal->dma_regs);
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return ESP_OK;
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}
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