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316 lines
10 KiB
C
316 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32h2/rom/cache.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
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#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
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#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
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#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4)
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#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4)
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#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
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#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
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#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
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#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
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#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
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#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
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/**
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* @brief Check if Cache auto preload is enabled or not.
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled = false;
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if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
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enabled = true;
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}
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return enabled;
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}
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/**
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* @brief Disable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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(void) type;
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Cache_Disable_ICache();
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}
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/**
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* @brief Enable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Suspend Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Suspend_ICache();
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}
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/**
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* @brief Resume Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Invalidate cache supported addr
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*
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* Invalidate a cache item
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param vaddr start address of the region to be invalidated
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* @param size size of the region to be invalidated
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*/
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__attribute__((always_inline))
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static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
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{
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Cache_Invalidate_Addr(vaddr, size);
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}
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/**
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* @brief Freeze Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
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}
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/**
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* @brief Unfreeze Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Freeze_ICache_Disable();
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}
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/**
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* @brief Get Cache line size, in bytes
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return Cache line size, in bytes
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*/
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__attribute__((always_inline))
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static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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uint32_t size = 0;
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size = Cache_Get_ICache_Line_Size();
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return size;
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}
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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cache_bus_mask_t mask = (cache_bus_mask_t)0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
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//h2 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
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mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
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} else {
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HAL_ASSERT(0); //Out of region
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}
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return mask;
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}
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
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REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
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REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be disabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
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REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
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REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
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}
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/**
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* @brief Get Cache level and the ID of the vaddr
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*
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* @param vaddr_start virtual address start
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* @param len vaddr length
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* @param out_level cache level
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* @param out_id cache id
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*
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* @return true for valid
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
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{
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bool valid = false;
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uint32_t vaddr_end = vaddr_start + len - 1;
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valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
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valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
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if (valid) {
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*out_level = 1;
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*out_id = 0;
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}
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return valid;
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}
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/*------------------------------------------------------------------------------
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* Interrupt
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*----------------------------------------------------------------------------*/
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/**
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* @brief Enable Cache access error interrupt
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*
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* @param cache_id Cache ID, not used on C3. For compabitlity
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
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{
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SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
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}
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/**
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* @brief Clear Cache access error interrupt status
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*
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* @param cache_id Cache ID, not used on C3. For compabitlity
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
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{
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SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
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}
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/**
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* @brief Get Cache access error interrupt status
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*
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* @param cache_id Cache ID, not used on C3. For compabitlity
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* @param mask Interrupt mask
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*
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* @return Status mask
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*/
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static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
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{
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return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
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}
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#ifdef __cplusplus
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}
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#endif
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