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145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "soc/soc_etm_struct.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the bus clock for ETM module
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*
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* @param group_id Group ID
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* @param enable true to enable, false to disable
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*/
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static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
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{
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(void)group_id;
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HP_SYS_CLKRST.soc_clk_ctrl3.reg_etm_apb_clk_en = enable;
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HP_SYS_CLKRST.soc_clk_ctrl1.reg_etm_sys_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the ETM module
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*
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* @param group_id Group ID
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*/
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static inline void etm_ll_reset_register(int group_id)
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{
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(void)group_id;
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_etm = 1;
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_etm = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define etm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_reset_register(__VA_ARGS__)
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/**
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* @brief Enable ETM channel
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*
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* @param hw ETM register base address
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* @param chan Channel ID
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*/
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static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
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{
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if (chan < 32) {
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hw->ch_ena_ad0_set.val = 1 << chan;
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} else {
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hw->ch_ena_ad1_set.val = 1 << (chan - 32);
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}
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}
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/**
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* @brief Disable ETM channel
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*
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* @param hw ETM register base address
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* @param chan Channel ID
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*/
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static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
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{
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if (chan < 32) {
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hw->ch_ena_ad0_clr.val = 1 << chan;
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} else {
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hw->ch_ena_ad1_clr.val = 1 << (chan - 32);
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}
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}
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/**
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* @brief Check whether the ETM channel is enabled or not
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*
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* @param hw ETM register base address
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* @param chan Channel ID
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* @return true if the channel is enabled, false otherwise
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*/
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static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
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{
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if (chan < 32) {
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return hw->ch_ena_ad0.val & (1 << chan);
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} else {
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return hw->ch_ena_ad1.val & (1 << (chan - 32));
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}
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}
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/**
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* @brief Set the input event for the ETM channel
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*
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* @param hw ETM register base address
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* @param chan Channel ID
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* @param event Event ID
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*/
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static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event);
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}
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/**
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* @brief Set the output task for the ETM channel
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*
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* @param hw ETM register base address
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* @param chan Channel ID
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* @param task Task ID
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*/
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static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task);
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}
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/**
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* @brief Get the flag that marks whether LP CPU is awakened by ETM
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*
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* @return Return true if lpcore is woken up by soc etm flag
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*/
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static inline bool etm_ll_is_lpcore_wakeup_triggered(void)
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{
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return SOC_ETM.task_st5.ulp_task_wakeup_cpu_st;
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}
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/**
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* @brief Clear the flag that marks whether LP CPU is awakened by ETM
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*/
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static inline void etm_ll_clear_lpcore_wakeup_status(void)
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{
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SOC_ETM.task_st5_clr.ulp_task_wakeup_cpu_st_clr = 1;
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}
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#ifdef __cplusplus
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}
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#endif
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