Omar Chebib 824552e9b4 RISC-V: fix usage of special register when interrupts are enabled

2021-12-21 01:06:11 +00:00

..

include

Security: ESP32C3 memory protection feature (IRAM0/DRAM0)

2021-01-27 08:44:03 +01:00

CMakeLists.txt

arch: move stdatomic

2021-11-02 16:24:18 +01:00

expression_with_stack_riscv_asm.S

core: fix cases where riscv SP were not 16 byte aligned

2021-06-02 16:02:10 +08:00

expression_with_stack_riscv.c

core: fix cases where riscv SP were not 16 byte aligned

2021-06-02 16:02:10 +08:00

instruction_decode.c

interrupt: filter out reserved int number by decoding risc-v JAL instruction

2021-01-05 15:39:46 +08:00

interrupt.c

interrupt: removed descriptor table from esp32c3 interrupt hal.

2021-01-05 15:39:46 +08:00

linker.lf

arch: move stdatomic

2021-11-02 16:24:18 +01:00

stdatomic.c

stdatomic: Implemented legacy __sync APIs and __atomic_exchange_n

2021-04-27 13:34:54 +05:30

vectors.S

RISC-V: fix usage of special register when interrupts are enabled

2021-12-21 01:06:11 +00:00