mirror of
https://github.com/espressif/esp-idf.git
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80910be77a
This commit removes the disabling of the LP Timer interrupt from the bootloader clock configuration routine. This allows the LP Timer interrupt to be visible to the LP Core after HP CPU boots up. Closes https://github.com/espressif/esp-idf/issues/15751
168 lines
10 KiB
C
168 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // TODO: IDF-5645
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#include "soc/rtc_cntl_reg.h"
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#else
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#include "soc/lp_wdt_reg.h"
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#include "soc/lp_timer_reg.h"
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#include "soc/lp_analog_peri_reg.h"
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#include "soc/pmu_reg.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C5
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#include "hal/clk_tree_ll.h"
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#endif
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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__attribute__((weak)) void bootloader_clock_configure(void)
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{
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// ROM bootloader may have put a lot of text into UART0 FIFO.
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// Wait for it to be printed.
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// This is not needed on power on reset, when ROM bootloader is running at
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// 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
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// and will be done with the bootloader much earlier than UART FIFO is empty.
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esp_rom_output_tx_wait_idle(0);
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/* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
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int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
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#if CONFIG_IDF_TARGET_ESP32
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/* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
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* 240 MHz may cause the chip to lock up (see section 3.5 of the errata
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* document). For rev. 0, switch to 240 instead if it has been enabled
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* previously.
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*/
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if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100) &&
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clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
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cpu_freq_mhz = 240;
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}
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#endif
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if (esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW || rtc_clk_apb_freq_get() < APB_CLK_FREQ) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
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// Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
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// RTC_SLOW clock source will be switched according to Kconfig selection at application startup
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clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
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if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
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clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
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}
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// Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader
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// RTC_FAST clock source will be switched to RC_FAST at application startup
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clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
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if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
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clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_DEFAULT;
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}
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#if CONFIG_IDF_TARGET_ESP32C6
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if (efuse_hal_chip_revision() == 0) {
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// Some of ESP32C6-ECO0 chip's SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue,
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// which will cause the chip to be unable to capture the reset reason when it is reset.
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// Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
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clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
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}
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#endif
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rtc_clk_init(clk_cfg);
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}
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/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
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* it here. Usually it needs some time to start up, so we amortize at least
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* part of the start up time by enabling 32k XTAL early.
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* App startup code will wait until the oscillator has started up.
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*/
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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if (!rtc_clk_32k_enabled()) {
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rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
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}
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#endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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// TODO: IDF-8938 Need refactor! Does not belong to clock configuration.
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
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#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
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#define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG LP_ANA_LP_INT_ENA_REG
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#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA LP_ANA_BOD_MODE0_LP_INT_ENA
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#define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG LP_ANA_LP_INT_CLR_REG
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#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR LP_ANA_BOD_MODE0_LP_INT_CLR
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#endif
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// CLR ENA
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
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CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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#elif CONFIG_IDF_TARGET_ESP32H2
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// CLR ENA
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
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CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
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#elif CONFIG_IDF_TARGET_ESP32H21
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// CLR ENA
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
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CLEAR_PERI_REG_MASK(LP_ANA_LP_INT_ENA_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR);
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#elif CONFIG_IDF_TARGET_ESP32H4
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// CLR ENA
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
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// TODO [ESP32H4] IDF-12295
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// CLEAR_PERI_REG_MASK(LP_ANA_LP_INT_ENA_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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// TODO [ESP32H4] IDF-12295
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// SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR);
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#elif CONFIG_IDF_TARGET_ESP32P4
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// CLR ENA
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
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CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_INT_ENA_REG, LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_INT_CLR_REG); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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#else
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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#endif
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}
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