Marius Vikhammer c36dd7834f core: fix cases where riscv SP were not 16 byte aligned ...

RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.

2021-02-19 11:26:21 +08:00

..

include/freertos

CI: enable example builds for C3

2021-02-09 12:04:02 +08:00

port.c

system: enable shared stack watchpoint

2021-02-18 15:38:30 +08:00

portasm.S

core: fix cases where riscv SP were not 16 byte aligned

2021-02-19 11:26:21 +08:00