Sudeep Mohanty 099f648686 ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 ...

This commit fixes an issue where in the ULP RISC-V I2C example causes
a spurious wakeup of the main CPU because of a Trap signal when the ULP
core does not meet the wakeup threshold values. This was due to the fact
that the RTC_CNTL_COCPU_DONE signal was being set before the
RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V
core to not reset properly on each cycle.

Closes https://github.com/espressif/esp-idf/issues/10301

2022-12-27 07:44:26 +00:00

..

include

ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3

2022-09-05 10:21:43 +02:00

start.S

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

ulp_riscv_adc.c

ulp: migrate tests to pytest embedded

2022-08-03 09:36:17 +08:00

ulp_riscv_i2c.c

ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3

2022-09-05 10:21:43 +02:00

ulp_riscv_lock.c

ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.

2022-08-05 18:16:31 +08:00

ulp_riscv_print.c

Add ULP-RISCV print and bitbanged UART tx API

2022-07-29 12:18:01 +08:00

ulp_riscv_uart.c

Add ULP-RISCV print and bitbanged UART tx API

2022-07-29 12:18:01 +08:00

ulp_riscv_utils.c

ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2

2022-12-27 07:44:26 +00:00