Ivan Grokhotkov 43b5fdd5c9 soc/rtc: fix switching between 80/160 and 240MHz ...

Previous code contained a check for PLL frequency to be 240MHz, while
in fact 240MHz was a CPU frequency; corresponding PLL frequency is
480MHz. Fixed the comparison and replaced integer MHz values with an
enum.

2018-03-27 10:55:59 +08:00

..

include/soc

bugfix/rtc_clk_32k_bootstrap: Fix starting 32k RTC

2018-03-21 13:27:56 +05:00

test

soc/rtc: run 32k XTAL startup test only in PSRAM config

2018-03-26 10:14:13 +08:00

cpu_util.c

esp_restart: fix possible race while stalling other CPU, enable WDT early

2017-10-26 19:53:53 +08:00

i2c_apll.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

i2c_bbpll.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

i2c_rtc_clk.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

rtc_clk.c

soc/rtc: fix switching between 80/160 and 240MHz

2018-03-27 10:55:59 +08:00

rtc_init.c

esp_adc_cal/Add eFuse functionality

2018-02-13 21:22:48 +08:00

rtc_pm.c

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

rtc_sleep.c

soc/rtc: add function to get/set VDDSDIO configuration

2017-11-03 15:49:09 +08:00

rtc_time.c

soc/rtc: add a function to wait for slow clock cycle

2017-10-26 19:53:53 +08:00

soc_log.h

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

soc_memory_layout.c

Add logic to make external RAM usable with malloc()

2017-09-28 17:17:50 +08:00