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https://github.com/espressif/esp-idf.git
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457ce080ae
Refactor the AES driver and add HAL, LL and caps. Add better support for running AES-GCM fully in hardware.
138 lines
3.5 KiB
C
138 lines
3.5 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "soc/hwcrypto_reg.h"
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#include "soc/dport_access.h"
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#include "hal/aes_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief State of AES accelerator, busy or idle
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*
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*/
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typedef enum {
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ESP_AES_STATE_BUSY = 0, /* Transform in progress */
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ESP_AES_STATE_IDLE, /* AES accelerator is idle */
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} esp_aes_state_t;
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/**
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* @brief Write the encryption/decryption key to hardware
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*
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* @param key Key to be written to the AES hardware
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* @param key_word_len Number of words in the key
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*
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* @return Number of bytes written to hardware, used for fault injection check,
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* if a write was skipped then this sum is likely to be wrong
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*/
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static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len)
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{
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/* This variable is used for fault injection checks, so marked volatile to avoid optimisation */
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volatile uint8_t key_bytes_in_hardware = 0;
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uint32_t *key_words = (uint32_t *)key;
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for (int i = 0; i < key_word_len; i++) {
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DPORT_REG_WRITE(AES_KEY_BASE + i * 4, *(key_words + i));
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key_bytes_in_hardware += 4;
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}
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return key_bytes_in_hardware;
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}
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/**
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* @brief Sets the mode
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*
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* @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0
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* @param key_bytes Number of bytes in the key
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*/
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static inline void aes_ll_set_mode(int mode, uint8_t key_bytes)
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{
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const uint32_t MODE_DECRYPT_BIT = 4;
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unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT;
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/* See TRM for the mapping between keylength and mode bit */
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DPORT_REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
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}
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/**
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* @brief Writes message block to AES hardware
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*
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* @param input Block to be written
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*/
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static inline void aes_ll_write_block(const uint8_t *input)
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{
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const uint32_t *input_words = (const uint32_t *)input;
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uint32_t i0;
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uint32_t i1;
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uint32_t i2;
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uint32_t i3;
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/* Storing i0,i1,i2,i3 in registers not an array
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helps a lot with optimisations at -Os level */
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i0 = input_words[0];
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DPORT_REG_WRITE(AES_TEXT_BASE, i0);
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i1 = input_words[1];
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DPORT_REG_WRITE(AES_TEXT_BASE + 4, i1);
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i2 = input_words[2];
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DPORT_REG_WRITE(AES_TEXT_BASE + 8, i2);
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i3 = input_words[3];
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DPORT_REG_WRITE(AES_TEXT_BASE + 12, i3);
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}
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/**
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* @brief Read the AES block
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*
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* @note If a transform was ran then this is the output
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*
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* @param output the output of the transform, length = AES_BLOCK_BYTES
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*/
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static inline void aes_ll_read_block(void *output)
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{
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uint32_t *output_words = (uint32_t *)output;
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esp_dport_access_read_buffer(output_words, AES_TEXT_BASE, AES_BLOCK_WORDS);
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}
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/**
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* @brief Starts block transform
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*
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*/
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static inline void aes_ll_start_transform(void)
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{
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DPORT_REG_WRITE(AES_START_REG, 1);
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}
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/**
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* @brief Read state of AES accelerator
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*
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* @return esp_aes_state_t
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*/
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static inline esp_aes_state_t aes_ll_get_state(void)
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{
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return DPORT_REG_READ(AES_IDLE_REG);
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}
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#ifdef __cplusplus
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}
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#endif
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