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			129 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			129 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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 *
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 * SPDX-License-Identifier: Apache-2.0
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 */
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#include <string.h>
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#include "esp_err.h"
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#include "mbedtls/aes.h"
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#include "esp_crypto_dma.h"
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#include "hal/clk_gate_ll.h"
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#include "hal/gdma_ll.h"
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#include "hal/gdma_types.h"
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#include "hal/aes_hal.h"
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#include "soc/lldesc.h"
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#include "soc/periph_defs.h"
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#include "soc/gdma_channel.h"
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#include "soc/gdma_struct.h"
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#include "soc/soc_caps.h"
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#define TEE_CRYPTO_GDMA_CH  (0)
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/*
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 * NOTE: [ESP-TEE] This is a low-level (LL), non-OS version of
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 * port/crypto_shared_gdma/esp_crypto_shared_gdma.c that defines
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 * the shared DMA layer for the AES and SHA peripherals for ESP-TEE.
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 */
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/* ---------------------------------------------- Shared GDMA layer for AES/SHA crypto ------------------------------------------------- */
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static void crypto_shared_gdma_init(void)
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{
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    // enable APB to access GDMA registers
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    periph_ll_enable_clk_clear_rst(PERIPH_GDMA_MODULE);
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    // enable gdma clock
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    gdma_ll_force_enable_reg_clock(&GDMA, true);
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    // setting the transfer ability
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    gdma_ll_tx_enable_data_burst(&GDMA, TEE_CRYPTO_GDMA_CH, true);
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    gdma_ll_tx_enable_descriptor_burst(&GDMA, TEE_CRYPTO_GDMA_CH, true);
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    gdma_ll_rx_enable_data_burst(&GDMA, TEE_CRYPTO_GDMA_CH, false);
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    gdma_ll_rx_enable_descriptor_burst(&GDMA, TEE_CRYPTO_GDMA_CH, true);
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#if SOC_GDMA_SUPPORT_PSRAM
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    gdma_ll_tx_set_block_size_psram(&GDMA, TEE_CRYPTO_GDMA_CH, GDMA_LL_EXT_MEM_BK_SIZE_16B);
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    gdma_ll_rx_set_block_size_psram(&GDMA, TEE_CRYPTO_GDMA_CH, GDMA_LL_EXT_MEM_BK_SIZE_16B);
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#endif // SOC_GDMA_SUPPORT_PSRAM
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    gdma_ll_tx_reset_channel(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_tx_connect_to_periph(&GDMA, TEE_CRYPTO_GDMA_CH, GDMA_TRIG_PERIPH_M2M, SOC_GDMA_TRIG_PERIPH_M2M0);
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    gdma_ll_rx_reset_channel(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_rx_connect_to_periph(&GDMA, TEE_CRYPTO_GDMA_CH, GDMA_TRIG_PERIPH_M2M, SOC_GDMA_TRIG_PERIPH_M2M0);
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}
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esp_err_t esp_tee_crypto_shared_gdma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t periph)
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{
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    int periph_inst_id = SOC_GDMA_TRIG_PERIPH_M2M0;
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    if (periph == GDMA_TRIG_PERIPH_SHA) {
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        periph_inst_id = SOC_GDMA_TRIG_PERIPH_SHA0;
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    } else if (periph == GDMA_TRIG_PERIPH_AES) {
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        periph_inst_id = SOC_GDMA_TRIG_PERIPH_AES0;
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    } else {
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        return ESP_ERR_INVALID_ARG;
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    }
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    crypto_shared_gdma_init();
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    gdma_ll_tx_disconnect_from_periph(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_rx_disconnect_from_periph(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_tx_reset_channel(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_tx_connect_to_periph(&GDMA, TEE_CRYPTO_GDMA_CH, periph, periph_inst_id);
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    gdma_ll_rx_reset_channel(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_rx_connect_to_periph(&GDMA, TEE_CRYPTO_GDMA_CH, periph, periph_inst_id);
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    gdma_ll_tx_set_desc_addr(&GDMA, TEE_CRYPTO_GDMA_CH, (intptr_t)input);
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    gdma_ll_tx_start(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_rx_set_desc_addr(&GDMA, TEE_CRYPTO_GDMA_CH, (intptr_t)output);
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    gdma_ll_rx_start(&GDMA, TEE_CRYPTO_GDMA_CH);
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    return ESP_OK;
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}
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void esp_tee_crypto_shared_gdma_free(void)
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{
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    gdma_ll_tx_stop(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_rx_stop(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_tx_disconnect_from_periph(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_rx_disconnect_from_periph(&GDMA, TEE_CRYPTO_GDMA_CH);
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    gdma_ll_tx_set_priority(&GDMA, TEE_CRYPTO_GDMA_CH, 0);
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    gdma_ll_rx_set_priority(&GDMA, TEE_CRYPTO_GDMA_CH, 0);
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    // disable gdma clock
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    gdma_ll_force_enable_reg_clock(&GDMA, false);
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    // disable APB for GDMA registers
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    periph_ll_disable_clk_set_rst(PERIPH_GDMA_MODULE);
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}
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/* ---------------------------------------------- DMA Implementations: AES ------------------------------------------------- */
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esp_err_t esp_aes_dma_start(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output)
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{
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    return esp_tee_crypto_shared_gdma_start(input, output, GDMA_TRIG_PERIPH_AES);
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}
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bool esp_aes_dma_done(crypto_dma_desc_t *output)
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{
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    return (output->dw0.owner == 0);
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}
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/* ---------------------------------------------- DMA Implementations: SHA ------------------------------------------------- */
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esp_err_t esp_sha_dma_start(const crypto_dma_desc_t *input)
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{
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    return esp_tee_crypto_shared_gdma_start(input, NULL, GDMA_TRIG_PERIPH_SHA);
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}
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