mirror of
https://github.com/espressif/esp-idf.git
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570 lines
16 KiB
C
570 lines
16 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/* INTERNAL API
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* implementation of PMS memory protection features
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*/
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#include <stdio.h>
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#include "sdkconfig.h"
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#include "soc/sensitive_reg.h"
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#include "soc/dport_access.h"
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#include "soc/periph_defs.h"
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#include "esp_intr_alloc.h"
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#include "hal/memprot_ll.h"
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#include "esp32c3/memprot.h"
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#include "riscv/interrupt.h"
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#include "esp32c3/rom/ets_sys.h"
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extern int _iram_text_end;
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const char *esp_memprot_mem_type_to_str(mem_type_prot_t mem_type)
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{
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switch (mem_type) {
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case MEMPROT_NONE:
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return "NONE";
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case MEMPROT_IRAM0_SRAM:
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return "IRAM0_SRAM";
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case MEMPROT_DRAM0_SRAM:
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return "DRAM0_SRAM";
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case MEMPROT_ALL:
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return "ALL";
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default:
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return "UNKNOWN";
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}
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}
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const char *esp_memprot_split_line_to_str(split_line_t line_type)
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{
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switch (line_type) {
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case MEMPROT_IRAM0_DRAM0_SPLITLINE:
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return "MEMPROT_IRAM0_DRAM0_SPLITLINE";
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case MEMPROT_IRAM0_LINE_0_SPLITLINE:
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return "MEMPROT_IRAM0_LINE_0_SPLITLINE";
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case MEMPROT_IRAM0_LINE_1_SPLITLINE:
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return "MEMPROT_IRAM0_LINE_1_SPLITLINE";
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case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE:
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return "MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE";
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case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE:
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return "MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE";
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default:
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return "UNKNOWN";
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}
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}
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const char *esp_memprot_pms_to_str(pms_area_t area_type)
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{
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switch (area_type) {
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case MEMPROT_IRAM0_PMS_AREA_0:
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return "MEMPROT_IRAM0_PMS_AREA_0";
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case MEMPROT_IRAM0_PMS_AREA_1:
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return "MEMPROT_IRAM0_PMS_AREA_1";
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case MEMPROT_IRAM0_PMS_AREA_2:
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return "MEMPROT_IRAM0_PMS_AREA_2";
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case MEMPROT_IRAM0_PMS_AREA_3:
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return "MEMPROT_IRAM0_PMS_AREA_3";
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case MEMPROT_DRAM0_PMS_AREA_0:
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return "MEMPROT_DRAM0_PMS_AREA_0";
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case MEMPROT_DRAM0_PMS_AREA_1:
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return "MEMPROT_DRAM0_PMS_AREA_1";
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case MEMPROT_DRAM0_PMS_AREA_2:
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return "MEMPROT_DRAM0_PMS_AREA_2";
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case MEMPROT_DRAM0_PMS_AREA_3:
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return "MEMPROT_DRAM0_PMS_AREA_3";
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default:
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return "UNKNOWN";
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}
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}
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/* split lines */
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void *esp_memprot_get_default_main_split_addr()
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{
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return &_iram_text_end;
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}
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uint32_t *esp_memprot_get_split_addr(split_line_t line_type)
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{
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switch ( line_type ) {
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case MEMPROT_IRAM0_DRAM0_SPLITLINE:
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return memprot_ll_get_iram0_split_line_main_I_D();
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case MEMPROT_IRAM0_LINE_0_SPLITLINE:
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return memprot_ll_get_iram0_split_line_I_0();
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case MEMPROT_IRAM0_LINE_1_SPLITLINE:
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return memprot_ll_get_iram0_split_line_I_1();
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case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE:
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return memprot_ll_get_dram0_split_line_D_0();
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case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE:
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return memprot_ll_get_dram0_split_line_D_1();
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default:
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abort();
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}
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}
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void esp_memprot_set_split_line_lock()
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{
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memprot_ll_set_iram0_dram0_split_line_lock();
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}
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bool esp_memprot_get_split_line_lock()
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{
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return memprot_ll_get_iram0_dram0_split_line_lock();
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}
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void esp_memprot_set_split_line(split_line_t line_type, const void *line_addr)
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{
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//split-line must be divisible by 512 (PMS module restriction)
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assert( ((uint32_t)line_addr) % 0x200 == 0 );
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switch ( line_type ) {
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case MEMPROT_IRAM0_DRAM0_SPLITLINE:
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memprot_ll_set_iram0_split_line_main_I_D(line_addr);
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break;
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case MEMPROT_IRAM0_LINE_0_SPLITLINE:
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memprot_ll_set_iram0_split_line_I_0(line_addr);
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break;
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case MEMPROT_IRAM0_LINE_1_SPLITLINE:
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memprot_ll_set_iram0_split_line_I_1(line_addr);
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break;
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case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE:
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memprot_ll_set_dram0_split_line_D_0(line_addr);
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break;
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case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE:
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memprot_ll_set_dram0_split_line_D_1(line_addr);
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break;
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default:
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abort();
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}
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}
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/* PMS */
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void esp_memprot_set_pms_lock(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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memprot_ll_iram0_set_pms_lock();
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break;
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case MEMPROT_DRAM0_SRAM:
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memprot_ll_dram0_set_pms_lock();
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break;
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default:
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abort();
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}
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}
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bool esp_memprot_get_pms_lock(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_pms_lock();
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_pms_lock();
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default:
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abort();
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}
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}
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void esp_memprot_iram_set_pms_area(pms_area_t area_type, bool r, bool w, bool x)
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{
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switch ( area_type ) {
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case MEMPROT_IRAM0_PMS_AREA_0:
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memprot_ll_iram0_set_pms_area_0(r, w, x);
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break;
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case MEMPROT_IRAM0_PMS_AREA_1:
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memprot_ll_iram0_set_pms_area_1(r, w, x);
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break;
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case MEMPROT_IRAM0_PMS_AREA_2:
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memprot_ll_iram0_set_pms_area_2(r, w, x);
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break;
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case MEMPROT_IRAM0_PMS_AREA_3:
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memprot_ll_iram0_set_pms_area_3(r, w, x);
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break;
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default:
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abort();
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}
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}
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void esp_memprot_iram_get_pms_area(pms_area_t area_type, bool *r, bool *w, bool *x)
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{
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switch ( area_type ) {
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case MEMPROT_IRAM0_PMS_AREA_0:
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memprot_ll_iram0_get_pms_area_0(r, w, x);
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break;
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case MEMPROT_IRAM0_PMS_AREA_1:
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memprot_ll_iram0_get_pms_area_1(r, w, x);
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break;
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case MEMPROT_IRAM0_PMS_AREA_2:
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memprot_ll_iram0_get_pms_area_2(r, w, x);
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break;
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case MEMPROT_IRAM0_PMS_AREA_3:
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memprot_ll_iram0_get_pms_area_3(r, w, x);
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break;
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default:
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abort();
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}
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}
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void esp_memprot_dram_set_pms_area(pms_area_t area_type, bool r, bool w)
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{
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switch ( area_type ) {
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case MEMPROT_DRAM0_PMS_AREA_0:
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memprot_ll_dram0_set_pms_area_0(r, w);
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break;
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case MEMPROT_DRAM0_PMS_AREA_1:
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memprot_ll_dram0_set_pms_area_1(r, w);
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break;
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case MEMPROT_DRAM0_PMS_AREA_2:
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memprot_ll_dram0_set_pms_area_2(r, w);
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break;
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case MEMPROT_DRAM0_PMS_AREA_3:
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memprot_ll_dram0_set_pms_area_3(r, w);
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break;
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default:
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abort();
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}
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}
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void esp_memprot_dram_get_pms_area(pms_area_t area_type, bool *r, bool *w)
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{
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switch ( area_type ) {
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case MEMPROT_DRAM0_PMS_AREA_0:
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memprot_ll_dram0_get_pms_area_0(r, w);
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break;
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case MEMPROT_DRAM0_PMS_AREA_1:
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memprot_ll_dram0_get_pms_area_1(r, w);
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break;
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case MEMPROT_DRAM0_PMS_AREA_2:
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memprot_ll_dram0_get_pms_area_2(r, w);
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break;
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case MEMPROT_DRAM0_PMS_AREA_3:
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memprot_ll_dram0_get_pms_area_3(r, w);
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break;
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default:
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abort();
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}
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}
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/* monitor */
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void esp_memprot_set_monitor_lock(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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memprot_ll_iram0_set_monitor_lock();
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break;
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case MEMPROT_DRAM0_SRAM:
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memprot_ll_dram0_set_monitor_lock();
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break;
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default:
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abort();
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}
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}
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bool esp_memprot_get_monitor_lock(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_monitor_lock();
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_monitor_lock();
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default:
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abort();
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}
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}
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void esp_memprot_set_monitor_en(mem_type_prot_t mem_type, bool enable)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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memprot_ll_iram0_set_monitor_en(enable);
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break;
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case MEMPROT_DRAM0_SRAM:
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memprot_ll_dram0_set_monitor_en(enable);
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break;
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default:
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abort();
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}
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}
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bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_monitor_en();
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_monitor_en();
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default:
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abort();
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}
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}
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bool esp_memprot_is_intr_ena_any()
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{
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return esp_memprot_get_monitor_en(MEMPROT_IRAM0_SRAM) || esp_memprot_get_monitor_en(MEMPROT_DRAM0_SRAM);
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}
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void esp_memprot_monitor_clear_intr(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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memprot_ll_iram0_clear_monitor_intr();
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memprot_ll_iram0_reset_clear_monitor_intr();
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break;
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case MEMPROT_DRAM0_SRAM:
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memprot_ll_dram0_clear_monitor_intr();
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memprot_ll_dram0_reset_clear_monitor_intr();
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break;
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default:
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abort();
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}
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}
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mem_type_prot_t esp_memprot_get_active_intr_memtype()
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{
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if ( memprot_ll_iram0_get_monitor_status_intr() > 0 ) {
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return MEMPROT_IRAM0_SRAM;
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} else if ( memprot_ll_dram0_get_monitor_status_intr() ) {
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return MEMPROT_DRAM0_SRAM;
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}
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return MEMPROT_NONE;
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}
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bool esp_memprot_is_locked_any()
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{
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return
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esp_memprot_get_split_line_lock() ||
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esp_memprot_get_pms_lock(MEMPROT_IRAM0_SRAM) ||
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esp_memprot_get_pms_lock(MEMPROT_DRAM0_SRAM) ||
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esp_memprot_get_monitor_lock(MEMPROT_IRAM0_SRAM) ||
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esp_memprot_get_monitor_lock(MEMPROT_DRAM0_SRAM);
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}
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bool esp_memprot_get_violate_intr_on(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_monitor_status_intr() == 1;
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_monitor_status_intr() == 1;
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default:
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abort();
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}
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}
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uint32_t esp_memprot_get_violate_addr(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_monitor_status_fault_addr();
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_monitor_status_fault_addr();
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default:
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abort();
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}
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}
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pms_world_t esp_memprot_get_violate_world(mem_type_prot_t mem_type)
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{
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uint32_t world = 0;
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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world = memprot_ll_iram0_get_monitor_status_fault_world();
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break;
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case MEMPROT_DRAM0_SRAM:
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world = memprot_ll_dram0_get_monitor_status_fault_world();
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break;
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default:
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abort();
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}
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switch ( world ) {
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case 0x01: return MEMPROT_PMS_WORLD_0;
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case 0x10: return MEMPROT_PMS_WORLD_1;
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default: return MEMPROT_PMS_WORLD_INVALID;
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}
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}
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pms_operation_type_t esp_memprot_get_violate_wr(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_monitor_status_fault_wr() == 1 ? MEMPROT_PMS_OP_WRITE : MEMPROT_PMS_OP_READ;
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_monitor_status_fault_wr() == 1 ? MEMPROT_PMS_OP_WRITE : MEMPROT_PMS_OP_READ;
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default:
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abort();
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}
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}
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bool esp_memprot_get_violate_loadstore(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return memprot_ll_iram0_get_monitor_status_fault_loadstore() == 1;
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default:
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abort();
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}
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}
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uint32_t esp_memprot_get_violate_byte_en(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_DRAM0_SRAM:
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return memprot_ll_dram0_get_monitor_status_fault_byte_en();
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default:
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abort();
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}
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}
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int esp_memprot_intr_get_cpuid()
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{
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return PRO_CPU_NUM;
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}
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void esp_memprot_set_intr_matrix(mem_type_prot_t mem_type)
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{
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ESP_INTR_DISABLE(ETS_MEMPROT_ERR_INUM);
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switch (mem_type) {
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case MEMPROT_IRAM0_SRAM:
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intr_matrix_set(esp_memprot_intr_get_cpuid(), memprot_ll_iram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
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break;
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case MEMPROT_DRAM0_SRAM:
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intr_matrix_set(esp_memprot_intr_get_cpuid(), memprot_ll_dram0_get_intr_source_num(), ETS_MEMPROT_ERR_INUM);
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break;
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default:
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abort();
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}
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/* Set the type and priority to cache error interrupts. */
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esprv_intc_int_set_type(BIT(ETS_MEMPROT_ERR_INUM), INTR_TYPE_LEVEL);
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esprv_intc_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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ESP_INTR_ENABLE(ETS_MEMPROT_ERR_INUM);
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}
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void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask)
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{
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esp_memprot_set_prot_int(invoke_panic_handler, lock_feature, NULL, mem_type_mask);
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}
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void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask)
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{
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uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask;
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bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM;
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bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM;
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|
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if (required_mem_prot == MEMPROT_NONE) {
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return;
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}
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//disable protection
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if (use_iram0) {
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esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, false);
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}
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if (use_dram0) {
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esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, false);
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}
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|
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//panic handling
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if (invoke_panic_handler) {
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if (use_iram0) {
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esp_memprot_set_intr_matrix(MEMPROT_IRAM0_SRAM);
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}
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if (use_dram0) {
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esp_memprot_set_intr_matrix(MEMPROT_DRAM0_SRAM);
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}
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}
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|
|
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//set split lines (must-have for all mem_types)
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const void *line_addr = split_addr == NULL ? esp_memprot_get_default_main_split_addr() : split_addr;
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esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_1_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_0_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_IRAM0_DRAM0_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr)));
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esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr)));
|
|
|
|
//set permissions
|
|
if (required_mem_prot & MEMPROT_IRAM0_SRAM) {
|
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, true, false, true);
|
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, true, false, true);
|
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, true, false, true);
|
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, true, true, false);
|
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}
|
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if (required_mem_prot & MEMPROT_DRAM0_SRAM) {
|
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esp_memprot_dram_set_pms_area( MEMPROT_DRAM0_PMS_AREA_0, true, false );
|
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, true, true);
|
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, true, true);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, true, true);
|
|
}
|
|
|
|
//reenable protection
|
|
if (use_iram0) {
|
|
esp_memprot_monitor_clear_intr(MEMPROT_IRAM0_SRAM);
|
|
esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, true);
|
|
}
|
|
if (use_dram0) {
|
|
esp_memprot_monitor_clear_intr(MEMPROT_DRAM0_SRAM);
|
|
esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, true);
|
|
}
|
|
|
|
//lock if required
|
|
if (lock_feature) {
|
|
esp_memprot_set_split_line_lock();
|
|
if (use_iram0) {
|
|
esp_memprot_set_pms_lock(MEMPROT_IRAM0_SRAM);
|
|
esp_memprot_set_monitor_lock(MEMPROT_IRAM0_SRAM);
|
|
}
|
|
if (use_dram0) {
|
|
esp_memprot_set_pms_lock(MEMPROT_DRAM0_SRAM);
|
|
esp_memprot_set_monitor_lock(MEMPROT_DRAM0_SRAM);
|
|
}
|
|
}
|
|
}
|
|
|
|
uint32_t esp_memprot_get_dram_status_reg_1()
|
|
{
|
|
return memprot_ll_dram0_get_monitor_status_register_1();
|
|
}
|
|
|
|
uint32_t esp_memprot_get_dram_status_reg_2()
|
|
{
|
|
return memprot_ll_dram0_get_monitor_status_register_2();
|
|
}
|
|
|
|
uint32_t esp_memprot_get_iram_status_reg()
|
|
{
|
|
return memprot_ll_iram0_get_monitor_status_register();
|
|
}
|
|
|
|
uint32_t esp_memprot_get_monitor_enable_reg(mem_type_prot_t mem_type)
|
|
{
|
|
switch (mem_type) {
|
|
case MEMPROT_IRAM0_SRAM:
|
|
return memprot_ll_iram0_get_monitor_enable_register();
|
|
case MEMPROT_DRAM0_SRAM:
|
|
return memprot_ll_dram0_get_monitor_enable_register();
|
|
default:
|
|
abort();
|
|
}
|
|
}
|