mirror of
https://github.com/espressif/esp-idf.git
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e21ab0332b
Vanilla FreeRTOS expects applications to use one of the heap implementations provided by FreeRTOS (i.e., heap_x.c), where functions such as pvPortMalloc() and vPortFree() are defined in the heap implementation. However, ESP-IDF already provides its own heap implementation (i.e., esp_heap_caps.h). Thus, the pvPortMallc()/vPortFree() functions were previously overriden by macro to call esp_heap functions directly. This commit refactors the FreeRTOS port's heap as such: - Added a heap_idf.c that implements all of the heap related functions required by FreeRTOS source - All dynamic memory allocated by FreeRTOS is from internal memory. Thus, the FreeRTOS heap is the internal memory subset of the ESP-IDF heap. - Removed some old macros to reduce diff from upstream source code.
844 lines
34 KiB
C
844 lines
34 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <stdint.h>
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#include <string.h>
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#include "FreeRTOS.h"
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#include "task.h" //For vApplicationStackOverflowHook
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#include "portmacro.h"
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#include "spinlock.h"
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#include "xt_instr_macros.h"
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#include "xtensa/xtensa_context.h"
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#include "xtensa/corebits.h"
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#include "xtensa/config/core.h"
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#include "xtensa/config/core-isa.h"
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#include "xtensa/xtruntime.h"
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#include "esp_private/esp_int_wdt.h"
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#include "esp_private/systimer.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_attr.h"
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#include "esp_heap_caps.h"
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#include "esp_system.h"
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#include "esp_task.h"
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#include "esp_log.h"
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#include "esp_cpu.h"
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#include "esp_rom_sys.h"
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#include "esp_task_wdt.h"
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#include "esp_heap_caps_init.h"
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#include "esp_freertos_hooks.h"
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#include "esp_intr_alloc.h"
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#include "esp_memory_utils.h"
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#ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "hal/systimer_hal.h"
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#include "hal/systimer_ll.h"
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#endif // CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
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_Static_assert(portBYTE_ALIGNMENT == 16, "portBYTE_ALIGNMENT must be set to 16");
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/* ---------------------------------------------------- Variables ------------------------------------------------------
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* - Various variables used to maintain the FreeRTOS port's state. Used from both port.c and various .S files
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* - Constant offsets are used by assembly to jump to particular TCB members or a stack area (such as the CPSA). We use
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* C constants instead of preprocessor macros due to assembly lacking "offsetof()".
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* ------------------------------------------------------------------------------------------------------------------ */
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#if XCHAL_CP_NUM > 0
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/* Offsets used to navigate to a task's CPSA on the stack */
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const DRAM_ATTR uint32_t offset_pxEndOfStack = offsetof(StaticTask_t, pxDummy8);
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const DRAM_ATTR uint32_t offset_cpsa = XT_CP_SIZE; /* Offset to start of the CPSA area on the stack. See uxInitialiseStackCPSA(). */
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#if configNUM_CORES > 1
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/* Offset to TCB_t.uxCoreAffinityMask member. Used to pin unpinned tasks that use the FPU. */
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const DRAM_ATTR uint32_t offset_uxCoreAffinityMask = offsetof(StaticTask_t, uxDummy25);
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#if configUSE_CORE_AFFINITY != 1
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#error "configUSE_CORE_AFFINITY must be 1 on multicore targets with coprocessor support"
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#endif
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#endif /* configNUM_CORES > 1 */
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#endif /* XCHAL_CP_NUM > 0 */
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volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0}; // Indicates whether scheduler is running on a per-core basis
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unsigned int port_interruptNesting[portNUM_PROCESSORS] = {0}; // Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit
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//FreeRTOS SMP Locks
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portMUX_TYPE port_xTaskLock = portMUX_INITIALIZER_UNLOCKED;
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portMUX_TYPE port_xISRLock = portMUX_INITIALIZER_UNLOCKED;
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/* ------------------------------------------------ IDF Compatibility --------------------------------------------------
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* - These need to be defined for IDF to compile
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------------- Interrupts ------------------------
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BaseType_t IRAM_ATTR xPortInterruptedFromISRContext(void)
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{
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return (port_interruptNesting[xPortGetCoreID()] != 0);
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}
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// ------------------ Critical Sections --------------------
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/*
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Variables used by IDF critical sections only (SMP tracks critical nesting inside TCB now)
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[refactor-todo] Figure out how IDF critical sections will be merged with SMP FreeRTOS critical sections
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*/
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BaseType_t port_uxCriticalNestingIDF[portNUM_PROCESSORS] = {0};
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BaseType_t port_uxCriticalOldInterruptStateIDF[portNUM_PROCESSORS] = {0};
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/*
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*******************************************************************************
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* Interrupt stack. The size of the interrupt stack is determined by the config
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* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
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*******************************************************************************
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*/
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volatile StackType_t DRAM_ATTR __attribute__((aligned(16))) port_IntStack[portNUM_PROCESSORS][configISR_STACK_SIZE];
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/* One flag for each individual CPU. */
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volatile uint32_t port_switch_flag[portNUM_PROCESSORS];
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BaseType_t xPortEnterCriticalTimeout(portMUX_TYPE *lock, BaseType_t timeout)
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{
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/* Interrupts may already be disabled (if this function is called in nested
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* manner). However, there's no atomic operation that will allow us to check,
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* thus we have to disable interrupts again anyways.
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*
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* However, if this is call is NOT nested (i.e., the first call to enter a
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* critical section), we will save the previous interrupt level so that the
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* saved level can be restored on the last call to exit the critical.
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*/
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BaseType_t xOldInterruptLevel = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
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if (!spinlock_acquire(lock, timeout)) {
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//Timed out attempting to get spinlock. Restore previous interrupt level and return
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XTOS_RESTORE_JUST_INTLEVEL((int) xOldInterruptLevel);
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return pdFAIL;
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}
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//Spinlock acquired. Increment the IDF critical nesting count.
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BaseType_t coreID = xPortGetCoreID();
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BaseType_t newNesting = port_uxCriticalNestingIDF[coreID] + 1;
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port_uxCriticalNestingIDF[coreID] = newNesting;
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//If this is the first entry to a critical section. Save the old interrupt level.
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if ( newNesting == 1 ) {
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port_uxCriticalOldInterruptStateIDF[coreID] = xOldInterruptLevel;
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}
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return pdPASS;
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}
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void vPortExitCriticalIDF(portMUX_TYPE *lock)
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{
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/* This function may be called in a nested manner. Therefore, we only need
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* to reenable interrupts if this is the last call to exit the critical. We
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* can use the nesting count to determine whether this is the last exit call.
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*/
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spinlock_release(lock);
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BaseType_t coreID = xPortGetCoreID();
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BaseType_t nesting = port_uxCriticalNestingIDF[coreID];
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if (nesting > 0) {
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nesting--;
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port_uxCriticalNestingIDF[coreID] = nesting;
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//This is the last exit call, restore the saved interrupt level
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if ( nesting == 0 ) {
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XTOS_RESTORE_JUST_INTLEVEL((int) port_uxCriticalOldInterruptStateIDF[coreID]);
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}
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}
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}
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/*
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In case any IDF libs called the port critical functions directly instead of through the macros.
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Just inline call the IDF versions
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*/
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void vPortEnterCritical(portMUX_TYPE *lock)
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{
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vPortEnterCriticalIDF(lock);
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}
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void vPortExitCritical(portMUX_TYPE *lock)
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{
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vPortExitCriticalIDF(lock);
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}
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// ----------------------- System --------------------------
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#define STACK_WATCH_POINT_NUMBER (SOC_CPU_WATCHPOINTS_NUM - 1)
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void vPortSetStackWatchpoint( void *pxStackStart )
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{
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//Set watchpoint 1 to watch the last 32 bytes of the stack.
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//Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because
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//the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32
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//bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most
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//28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes.
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//This way, we make sure we trigger before/when the stack canary is corrupted, not after.
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int addr = (int)pxStackStart;
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addr = (addr + 31) & (~31);
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esp_cpu_set_watchpoint(STACK_WATCH_POINT_NUMBER, (char *)addr, 32, ESP_CPU_WATCHPOINT_STORE);
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}
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// ---------------------- Tick Timer -----------------------
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BaseType_t xPortSysTickHandler(void);
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#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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extern void _frxt_tick_timer_init(void);
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extern void _xt_tick_divisor_init(void);
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#ifdef CONFIG_FREERTOS_CORETIMER_0
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#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
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#endif
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#ifdef CONFIG_FREERTOS_CORETIMER_1
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#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
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#endif
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/**
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* @brief Initialize CCONT timer to generate the tick interrupt
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*
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*/
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void vPortSetupTimer(void)
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{
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/* Init the tick divisor value */
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_xt_tick_divisor_init();
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_frxt_tick_timer_init();
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}
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#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
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_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");
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void SysTickIsrHandler(void *arg);
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static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
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#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
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/**
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* @brief Set up the systimer peripheral to generate the tick interrupt
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*
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* Both timer alarms are configured in periodic mode.
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* It is done at the same time so SysTicks for both CPUs occur at the same time or very close.
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* Shifts a time of triggering interrupts for core 0 and core 1.
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*/
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void vPortSetupTimer(void)
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{
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unsigned cpuid = xPortGetCoreID();
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#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
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const unsigned level = ESP_INTR_FLAG_LEVEL3;
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#else
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const unsigned level = ESP_INTR_FLAG_LEVEL1;
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#endif
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/* Systimer HAL layer object */
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static systimer_hal_context_t systimer_hal;
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/* set system timer interrupt vector */
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
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if (cpuid == 0) {
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periph_module_enable(PERIPH_SYSTIMER_MODULE);
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systimer_hal_init(&systimer_hal);
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systimer_hal_tick_rate_ops_t ops = {
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.ticks_to_us = systimer_ticks_to_us,
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.us_to_ticks = systimer_us_to_ticks,
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};
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systimer_hal_set_tick_rate_ops(&systimer_hal, &ops);
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systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_COUNTER_OS_TICK, 0);
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systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_COUNTER_OS_TICK);
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for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) {
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systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_COUNTER_OS_TICK, cpuid, false);
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}
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for (cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid) {
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uint32_t alarm_id = SYSTIMER_ALARM_OS_TICK_CORE0 + cpuid;
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/* configure the timer */
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systimer_hal_connect_alarm_counter(&systimer_hal, alarm_id, SYSTIMER_COUNTER_OS_TICK);
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systimer_hal_set_alarm_period(&systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ);
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systimer_hal_select_alarm_mode(&systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD);
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systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_COUNTER_OS_TICK, cpuid, true);
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if (cpuid == 0) {
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systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
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systimer_hal_enable_counter(&systimer_hal, SYSTIMER_COUNTER_OS_TICK);
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#ifndef CONFIG_FREERTOS_UNICORE
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// SysTick of core 0 and core 1 are shifted by half of period
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systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2);
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#endif
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}
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}
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} else {
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uint32_t alarm_id = SYSTIMER_ALARM_OS_TICK_CORE0 + cpuid;
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systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
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}
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}
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/**
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* @brief Systimer interrupt handler.
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*
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* The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm.
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* If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks.
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*/
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IRAM_ATTR void SysTickIsrHandler(void *arg)
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{
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uint32_t cpuid = xPortGetCoreID();
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systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg;
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#ifdef CONFIG_PM_TRACE
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ESP_PM_TRACE_ENTER(TICK, cpuid);
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#endif
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uint32_t alarm_id = SYSTIMER_ALARM_OS_TICK_CORE0 + cpuid;
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do {
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systimer_ll_clear_alarm_int(systimer_hal->dev, alarm_id);
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uint32_t diff = systimer_hal_get_counter_value(systimer_hal, SYSTIMER_COUNTER_OS_TICK) / systimer_ll_get_alarm_period(systimer_hal->dev, alarm_id) - s_handled_systicks[cpuid];
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if (diff > 0) {
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if (s_handled_systicks[cpuid] == 0) {
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s_handled_systicks[cpuid] = diff;
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diff = 1;
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} else {
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s_handled_systicks[cpuid] += diff;
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}
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do {
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xPortSysTickHandler();
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} while (--diff);
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}
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} while (systimer_ll_is_alarm_int_fired(systimer_hal->dev, alarm_id));
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#ifdef CONFIG_PM_TRACE
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ESP_PM_TRACE_EXIT(TICK, cpuid);
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#endif
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}
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#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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/* ---------------------------------------------- Port Implementations -------------------------------------------------
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* Implementations of Porting Interface functions
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------------- Interrupts ------------------------
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BaseType_t xPortCheckIfInISR(void)
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{
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//Disable interrupts so that reading port_interruptNesting is atomic
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BaseType_t ret;
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unsigned int prev_int_level = portDISABLE_INTERRUPTS();
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ret = (port_interruptNesting[xPortGetCoreID()] != 0) ? pdTRUE : pdFALSE;
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portRESTORE_INTERRUPTS(prev_int_level);
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return ret;
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}
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// ------------------ Critical Sections --------------------
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void vPortTakeLock( portMUX_TYPE *lock )
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{
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spinlock_acquire( lock, portMUX_NO_TIMEOUT);
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}
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void vPortReleaseLock( portMUX_TYPE *lock )
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{
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spinlock_release( lock );
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}
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// ---------------------- Yielding -------------------------
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// ----------------------- System --------------------------
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/* ------------------------------------------------ FreeRTOS Portable --------------------------------------------------
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* - Provides implementation for functions required by FreeRTOS
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* - Declared in portable.h
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* ------------------------------------------------------------------------------------------------------------------ */
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// ----------------- Scheduler Start/End -------------------
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extern void _xt_coproc_init(void);
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BaseType_t xPortStartScheduler( void )
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{
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portDISABLE_INTERRUPTS();
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// Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
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#if XCHAL_CP_NUM > 0
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/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
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_xt_coproc_init();
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#endif
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/* Setup the hardware to generate the tick. */
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vPortSetupTimer();
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port_xSchedulerRunning[xPortGetCoreID()] = 1;
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#if configNUM_CORES > 1
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// Workaround for non-thread safe multi-core OS startup (see IDF-4524)
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if (xPortGetCoreID() != 0) {
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vTaskStartSchedulerOtherCores();
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}
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#endif // configNUM_CORES > 1
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// Cannot be directly called from C; never returns
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__asm__ volatile ("call0 _frxt_dispatch\n");
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/* Should not get here. */
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return pdTRUE;
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}
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void vPortEndScheduler( void )
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{
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;
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}
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// ------------------------ Stack --------------------------
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// User exception dispatcher when exiting
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void _xt_user_exit(void);
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#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
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// Wrapper to allow task functions to return (increases stack overhead by 16 bytes)
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static void vPortTaskWrapper(TaskFunction_t pxCode, void *pvParameters)
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{
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pxCode(pvParameters);
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//FreeRTOS tasks should not return. Log the task name and abort.
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char *pcTaskName = pcTaskGetName(NULL);
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ESP_LOGE("FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName);
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abort();
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}
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#endif
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/**
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* @brief Align stack pointer in a downward growing stack
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*
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* This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2.
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* This macro is generally used when allocating aligned areas on a downward growing stack.
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*/
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#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1)))
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#if XCHAL_CP_NUM > 0
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/**
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* @brief Allocate and initialize coprocessor save area on the stack
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*
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* This function allocates the coprocessor save area on the stack (sized XT_CP_SIZE) which includes...
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* - Individual save areas for each coprocessor (size XT_CPx_SA, inclusive of each area's alignment)
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* - Coprocessor context switching flags (e.g., XT_CPENABLE, XT_CPSTORED, XT_CP_CS_ST, XT_CP_ASA).
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*
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* The coprocessor save area is aligned to a 16-byte boundary.
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* The coprocessor context switching flags are then initialized
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*
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* @param[in] uxStackPointer Current stack pointer address
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* @return Stack pointer that points to allocated and initialized the coprocessor save area
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*/
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FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackCPSA(UBaseType_t uxStackPointer)
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{
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/*
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HIGH ADDRESS
|
|
|-------------------| XT_CP_SIZE
|
|
| CPn SA | ^
|
|
| ... | |
|
|
| CP0 SA | |
|
|
| ----------------- | | ---- XCHAL_TOTAL_SA_ALIGN aligned
|
|
|-------------------| | 12 bytes
|
|
| XT_CP_ASA | | ^
|
|
| XT_CP_CS_ST | | |
|
|
| XT_CPSTORED | | |
|
|
| XT_CPENABLE | | |
|
|
|-------------------| ---------------------- 16 byte aligned
|
|
LOW ADDRESS
|
|
*/
|
|
|
|
// Allocate overall coprocessor save area, aligned down to 16 byte boundary
|
|
uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_CP_SIZE);
|
|
// Initialize the coprocessor context switching flags.
|
|
uint32_t *p = (uint32_t *)uxStackPointer;
|
|
p[0] = 0; // Clear XT_CPENABLE and XT_CPSTORED
|
|
p[1] = 0; // Clear XT_CP_CS_ST
|
|
// XT_CP_ASA points to the aligned start of the individual CP save areas (i.e., start of CP0 SA)
|
|
p[2] = (uint32_t)ALIGNUP(XCHAL_TOTAL_SA_ALIGN, (uint32_t)uxStackPointer + 12);
|
|
return uxStackPointer;
|
|
}
|
|
#endif /* XCHAL_CP_NUM > 0 */
|
|
|
|
/**
|
|
* @brief Allocate and initialize GCC TLS area
|
|
*
|
|
* This function allocates and initializes the area on the stack used to store GCC TLS (Thread Local Storage) variables.
|
|
* - The area's size is derived from the TLS section's linker variables, and rounded up to a multiple of 16 bytes
|
|
* - The allocated area is aligned to a 16-byte aligned address
|
|
* - The TLS variables in the area are then initialized
|
|
*
|
|
* Each task access the TLS variables using the THREADPTR register plus an offset to obtain the address of the variable.
|
|
* The value for the THREADPTR register is also calculated by this function, and that value should be use to initialize
|
|
* the THREADPTR register.
|
|
*
|
|
* @param[in] uxStackPointer Current stack pointer address
|
|
* @param[out] ret_threadptr_reg_init Calculated THREADPTR register initialization value
|
|
* @return Stack pointer that points to the TLS area
|
|
*/
|
|
FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, uint32_t *ret_threadptr_reg_init)
|
|
{
|
|
/*
|
|
TLS layout at link-time, where 0xNNN is the offset that the linker calculates to a particular TLS variable.
|
|
|
|
LOW ADDRESS
|
|
|---------------------------| Linker Symbols
|
|
| Section | --------------
|
|
| .flash.rodata |
|
|
0x0|---------------------------| <- _flash_rodata_start
|
|
^ | Other Data |
|
|
| |---------------------------| <- _thread_local_start
|
|
| | .tbss | ^
|
|
V | | |
|
|
0xNNN | int example; | | tls_area_size
|
|
| | |
|
|
| .tdata | V
|
|
|---------------------------| <- _thread_local_end
|
|
| Other data |
|
|
| ... |
|
|
|---------------------------|
|
|
HIGH ADDRESS
|
|
*/
|
|
// Calculate the TLS area's size (rounded up to multiple of 16 bytes).
|
|
extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align;
|
|
const uint32_t tls_area_size = ALIGNUP(16, (uint32_t)&_thread_local_end - (uint32_t)&_thread_local_start);
|
|
// TODO: check that TLS area fits the stack
|
|
|
|
// Allocate space for the TLS area on the stack. The area must be allocated at a 16-byte aligned address
|
|
uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size);
|
|
// Initialize the TLS area with the initialization values of each TLS variable
|
|
memcpy((void *)uxStackPointer, &_thread_local_start, tls_area_size);
|
|
|
|
/*
|
|
Calculate the THREADPTR register's initialization value based on the link-time offset and the TLS area allocated on
|
|
the stack.
|
|
|
|
HIGH ADDRESS
|
|
|---------------------------|
|
|
| .tdata (*) |
|
|
^ | int example; |
|
|
| | |
|
|
| | .tbss (*) |
|
|
| |---------------------------| <- uxStackPointer (start of TLS area)
|
|
0xNNN | | | ^
|
|
| | | |
|
|
| ... | (_thread_local_start - _flash_rodata_start) + align_up(TCB_SIZE, tls_section_alignment)
|
|
| | | |
|
|
| | | V
|
|
V | | <- threadptr register's value
|
|
|
|
LOW ADDRESS
|
|
|
|
Note: Xtensa is slightly different compared to the RISC-V port as there is an implicit aligned TCB_SIZE added to
|
|
the offset. (search for 'tpoff' in elf32-xtensa.c in BFD):
|
|
- "offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment)"
|
|
- TCB_SIZE is hardcoded to 8
|
|
*/
|
|
const uint32_t tls_section_align = (uint32_t)&_flash_rodata_align; // ALIGN value of .flash.rodata section
|
|
#define TCB_SIZE 8
|
|
const uint32_t base = ALIGNUP(tls_section_align, TCB_SIZE);
|
|
*ret_threadptr_reg_init = (uint32_t)uxStackPointer - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start) - base;
|
|
|
|
return uxStackPointer;
|
|
}
|
|
|
|
/**
|
|
* @brief Initialize the task's starting interrupt stack frame
|
|
*
|
|
* This function initializes the task's starting interrupt stack frame. The dispatcher will use this stack frame in a
|
|
* context restore routine. Therefore, the starting stack frame must be initialized as if the task was interrupted right
|
|
* before its first instruction is called.
|
|
*
|
|
* - The stack frame is allocated to a 16-byte aligned address
|
|
* - The THREADPTR register is saved in the extra storage area of the stack frame. This is also initialized
|
|
*
|
|
* @param[in] uxStackPointer Current stack pointer address
|
|
* @param[in] pxCode Task function
|
|
* @param[in] pvParameters Task function's parameter
|
|
* @param[in] threadptr_reg_init THREADPTR register initialization value
|
|
* @return Stack pointer that points to the stack frame
|
|
*/
|
|
FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, TaskFunction_t pxCode, void *pvParameters, uint32_t threadptr_reg_init)
|
|
{
|
|
/*
|
|
HIGH ADDRESS
|
|
|---------------------------| ^ XT_STK_FRMSZ
|
|
| | |
|
|
| Stack Frame Extra Storage | |
|
|
| | |
|
|
| ------------------------- | | ^ XT_STK_EXTRA
|
|
| | | |
|
|
| Intr/Exc Stack Frame | | |
|
|
| | V V
|
|
| ------------------------- | ---------------------- 16 byte aligned
|
|
LOW ADDRESS
|
|
*/
|
|
|
|
/*
|
|
Allocate space for the task's starting interrupt stack frame.
|
|
- The stack frame must be allocated to a 16-byte aligned address.
|
|
- We use XT_STK_FRMSZ (instead of sizeof(XtExcFrame)) as it...
|
|
- includes the size of the extra storage area
|
|
- includes the size for a base save area before the stack frame
|
|
- rounds up the total size to a multiple of 16
|
|
*/
|
|
UBaseType_t uxStackPointerPrevious = uxStackPointer;
|
|
uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_STK_FRMSZ);
|
|
|
|
// Clear the entire interrupt stack frame
|
|
memset((void *)uxStackPointer, 0, (size_t)(uxStackPointerPrevious - uxStackPointer));
|
|
|
|
XtExcFrame *frame = (XtExcFrame *)uxStackPointer;
|
|
|
|
/*
|
|
Initialize common registers
|
|
*/
|
|
frame->a0 = 0; // Set the return address to 0 terminate GDB backtrace
|
|
frame->a1 = uxStackPointer + XT_STK_FRMSZ; // Saved stack pointer should point to physical top of stack frame
|
|
frame->exit = (UBaseType_t) _xt_user_exit; // User exception exit dispatcher
|
|
|
|
/*
|
|
Initialize the task's entry point. This will differ depending on
|
|
- Whether the task's entry point is the wrapper function or pxCode
|
|
- Whether Windowed ABI is used (for windowed, we mimic the task entry point being call4'd )
|
|
*/
|
|
#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
|
|
frame->pc = (UBaseType_t) vPortTaskWrapper; // Task entry point is the wrapper function
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
frame->a2 = (UBaseType_t) pxCode; // Wrapper function's argument 0 (which is the task function)
|
|
frame->a3 = (UBaseType_t) pvParameters; // Wrapper function's argument 1 (which is the task function's argument)
|
|
#else // __XTENSA_CALL0_ABI__
|
|
frame->a6 = (UBaseType_t) pxCode; // Wrapper function's argument 0 (which is the task function), passed as if we call4'd
|
|
frame->a7 = (UBaseType_t) pvParameters; // Wrapper function's argument 1 (which is the task function's argument), passed as if we call4'd
|
|
#endif // __XTENSA_CALL0_ABI__
|
|
#else
|
|
frame->pc = (UBaseType_t) pxCode; // Task entry point is the provided task function
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
frame->a2 = (UBaseType_t) pvParameters; // Task function's argument
|
|
#else // __XTENSA_CALL0_ABI__
|
|
frame->a6 = (UBaseType_t) pvParameters; // Task function's argument, passed as if we call4'd
|
|
#endif // __XTENSA_CALL0_ABI__
|
|
#endif
|
|
|
|
/*
|
|
Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode.
|
|
For windowed ABI also set WOE and CALLINC (pretend task was 'call4'd)
|
|
*/
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
frame->ps = PS_UM | PS_EXCM;
|
|
#else // __XTENSA_CALL0_ABI__
|
|
frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
|
|
#endif // __XTENSA_CALL0_ABI__
|
|
|
|
#ifdef XT_USE_SWPRI
|
|
// Set the initial virtual priority mask value to all 1's.
|
|
frame->vpri = 0xFFFFFFFF;
|
|
#endif
|
|
|
|
// Initialize the threadptr register in the extra save area of the stack frame
|
|
uint32_t *threadptr_reg = (uint32_t *)(uxStackPointer + XT_STK_EXTRA);
|
|
*threadptr_reg = threadptr_reg_init;
|
|
|
|
return uxStackPointer;
|
|
}
|
|
|
|
#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
|
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
|
StackType_t * pxEndOfStack,
|
|
TaskFunction_t pxCode,
|
|
void * pvParameters )
|
|
#else
|
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
|
TaskFunction_t pxCode,
|
|
void * pvParameters )
|
|
#endif
|
|
{
|
|
#ifdef __clang_analyzer__
|
|
// Teach clang-tidy that pxTopOfStack cannot be a pointer to const
|
|
volatile StackType_t * pxTemp = pxTopOfStack;
|
|
pxTopOfStack = pxTemp;
|
|
#endif /*__clang_analyzer__ */
|
|
/*
|
|
HIGH ADDRESS
|
|
|---------------------------| <- pxTopOfStack on entry
|
|
| Coproc Save Area | (CPSA MUST BE FIRST)
|
|
| ------------------------- |
|
|
| TLS Variables |
|
|
| ------------------------- | <- Start of useable stack
|
|
| Starting stack frame |
|
|
| ------------------------- | <- pxTopOfStack on return (which is the tasks current SP)
|
|
| | |
|
|
| | |
|
|
| V |
|
|
----------------------------- <- Bottom of stack
|
|
LOW ADDRESS
|
|
|
|
- All stack areas are aligned to 16 byte boundary
|
|
- We use UBaseType_t for all of stack area initialization functions for more convenient pointer arithmetic
|
|
*/
|
|
|
|
UBaseType_t uxStackPointer = (UBaseType_t)pxTopOfStack;
|
|
configASSERT((uxStackPointer & portBYTE_ALIGNMENT_MASK) == 0);
|
|
|
|
#if XCHAL_CP_NUM > 0
|
|
// Initialize the coprocessor save area. THIS MUST BE THE FIRST AREA due to access from _frxt_task_coproc_state()
|
|
uxStackPointer = uxInitialiseStackCPSA(uxStackPointer);
|
|
configASSERT((uxStackPointer & portBYTE_ALIGNMENT_MASK) == 0);
|
|
#endif /* XCHAL_CP_NUM > 0 */
|
|
|
|
// Initialize the GCC TLS area
|
|
uint32_t threadptr_reg_init;
|
|
uxStackPointer = uxInitialiseStackTLS(uxStackPointer, &threadptr_reg_init);
|
|
configASSERT((uxStackPointer & portBYTE_ALIGNMENT_MASK) == 0);
|
|
|
|
// Initialize the starting interrupt stack frame
|
|
uxStackPointer = uxInitialiseStackFrame(uxStackPointer, pxCode, pvParameters, threadptr_reg_init);
|
|
configASSERT((uxStackPointer & portBYTE_ALIGNMENT_MASK) == 0);
|
|
|
|
// Return the task's current stack pointer address which should point to the starting interrupt stack frame
|
|
return (StackType_t *)uxStackPointer;
|
|
}
|
|
// -------------------- Co-Processor -----------------------
|
|
#if ( XCHAL_CP_NUM > 0 && configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 )
|
|
|
|
void _xt_coproc_release(volatile void *coproc_sa_base, BaseType_t xTargetCoreID);
|
|
|
|
void vPortCleanUpCoprocArea( void *pxTCB )
|
|
{
|
|
UBaseType_t uxCoprocArea;
|
|
BaseType_t xTargetCoreID;
|
|
|
|
/* Get pointer to the task's coprocessor save area from TCB->pxEndOfStack. See uxInitialiseStackCPSA() */
|
|
uxCoprocArea = ( UBaseType_t ) ( ( ( StaticTask_t * ) pxTCB )->pxDummy8 ); /* Get TCB_t.pxEndOfStack */
|
|
uxCoprocArea = STACKPTR_ALIGN_DOWN(16, uxCoprocArea - XT_CP_SIZE);
|
|
|
|
/* Extract core ID from the affinity mask */
|
|
xTargetCoreID = ( ( StaticTask_t * ) pxTCB )->uxDummy25 ;
|
|
xTargetCoreID = ( BaseType_t ) __builtin_ffs( ( int ) xTargetCoreID );
|
|
assert( xTargetCoreID >= 1 ); // __builtin_ffs always returns first set index + 1
|
|
xTargetCoreID -= 1;
|
|
|
|
/* If task has live floating point registers somewhere, release them */
|
|
_xt_coproc_release( (void *)uxCoprocArea, xTargetCoreID );
|
|
}
|
|
#endif // ( XCHAL_CP_NUM > 0 && configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 )
|
|
|
|
// ------- Thread Local Storage Pointers Deletion Callbacks -------
|
|
|
|
#if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS )
|
|
void vPortTLSPointersDelCb( void *pxTCB )
|
|
{
|
|
/* Typecast pxTCB to StaticTask_t type to access TCB struct members.
|
|
* pvDummy15 corresponds to pvThreadLocalStoragePointers member of the TCB.
|
|
*/
|
|
StaticTask_t *tcb = ( StaticTask_t * )pxTCB;
|
|
|
|
/* The TLSP deletion callbacks are stored at an offset of (configNUM_THREAD_LOCAL_STORAGE_POINTERS/2) */
|
|
TlsDeleteCallbackFunction_t *pvThreadLocalStoragePointersDelCallback = ( TlsDeleteCallbackFunction_t * )( &( tcb->pvDummy15[ ( configNUM_THREAD_LOCAL_STORAGE_POINTERS / 2 ) ] ) );
|
|
|
|
/* We need to iterate over half the depth of the pvThreadLocalStoragePointers area
|
|
* to access all TLS pointers and their respective TLS deletion callbacks.
|
|
*/
|
|
for ( int x = 0; x < ( configNUM_THREAD_LOCAL_STORAGE_POINTERS / 2 ); x++ ) {
|
|
if ( pvThreadLocalStoragePointersDelCallback[ x ] != NULL ) { //If del cb is set
|
|
/* In case the TLSP deletion callback has been overwritten by a TLS pointer, gracefully abort. */
|
|
if ( !esp_ptr_executable( pvThreadLocalStoragePointersDelCallback[ x ] ) ) {
|
|
// We call EARLY log here as currently portCLEAN_UP_TCB() is called in a critical section
|
|
ESP_EARLY_LOGE("FreeRTOS", "Fatal error: TLSP deletion callback at index %d overwritten with non-excutable pointer %p", x, pvThreadLocalStoragePointersDelCallback[ x ]);
|
|
abort();
|
|
}
|
|
|
|
pvThreadLocalStoragePointersDelCallback[ x ]( x, tcb->pvDummy15[ x ] ); //Call del cb
|
|
}
|
|
}
|
|
}
|
|
#endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS
|
|
|
|
// -------------------- Tick Handler -----------------------
|
|
|
|
extern void esp_vApplicationIdleHook(void);
|
|
extern void esp_vApplicationTickHook(void);
|
|
|
|
BaseType_t xPortSysTickHandler(void)
|
|
{
|
|
portbenchmarkIntLatency();
|
|
traceISR_ENTER(SYSTICK_INTR_ID);
|
|
BaseType_t ret;
|
|
esp_vApplicationTickHook();
|
|
if (portGET_CORE_ID() == 0) {
|
|
// FreeRTOS SMP requires that only core 0 calls xTaskIncrementTick()
|
|
ret = xTaskIncrementTick();
|
|
} else {
|
|
ret = pdFALSE;
|
|
}
|
|
if (ret != pdFALSE) {
|
|
portYIELD_FROM_ISR();
|
|
} else {
|
|
traceISR_EXIT();
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
// ------------------- Hook Functions ----------------------
|
|
|
|
#include <stdlib.h>
|
|
|
|
#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )
|
|
void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName )
|
|
{
|
|
#define ERR_STR1 "***ERROR*** A stack overflow in task "
|
|
#define ERR_STR2 " has been detected."
|
|
const char *str[] = {ERR_STR1, pcTaskName, ERR_STR2};
|
|
|
|
char buf[sizeof(ERR_STR1) + CONFIG_FREERTOS_MAX_TASK_NAME_LEN + sizeof(ERR_STR2) + 1 /* null char */] = { 0 };
|
|
|
|
char *dest = buf;
|
|
for (size_t i = 0 ; i < sizeof(str) / sizeof(str[0]); i++) {
|
|
dest = strcat(dest, str[i]);
|
|
}
|
|
esp_system_abort(buf);
|
|
}
|
|
#endif
|
|
|
|
#if CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK
|
|
/*
|
|
By default, the port uses vApplicationMinimalIdleHook() to run IDF style idle
|
|
hooks. However, users may also want to provide their own vApplicationMinimalIdleHook().
|
|
In this case, we use to -Wl,--wrap option to wrap the user provided vApplicationMinimalIdleHook()
|
|
*/
|
|
extern void __real_vApplicationMinimalIdleHook( void );
|
|
void __wrap_vApplicationMinimalIdleHook( void )
|
|
{
|
|
esp_vApplicationIdleHook(); //Run IDF style hooks
|
|
__real_vApplicationMinimalIdleHook(); //Call the user provided vApplicationMinimalIdleHook()
|
|
}
|
|
#else // CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK
|
|
void vApplicationMinimalIdleHook( void )
|
|
{
|
|
esp_vApplicationIdleHook(); //Run IDF style hooks
|
|
}
|
|
#endif // CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK
|
|
|
|
/*
|
|
* Hook function called during prvDeleteTCB() to cleanup any
|
|
* user defined static memory areas in the TCB.
|
|
*/
|
|
#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP
|
|
void __real_vPortCleanUpTCB( void *pxTCB );
|
|
|
|
void __wrap_vPortCleanUpTCB( void *pxTCB )
|
|
#else
|
|
void vPortCleanUpTCB ( void *pxTCB )
|
|
#endif /* CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP */
|
|
{
|
|
#if ( CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP )
|
|
/* Call user defined vPortCleanUpTCB */
|
|
__real_vPortCleanUpTCB( pxTCB );
|
|
#endif /* CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP */
|
|
|
|
#if ( CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS )
|
|
/* Call TLS pointers deletion callbacks */
|
|
vPortTLSPointersDelCb( pxTCB );
|
|
#endif /* CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS */
|
|
|
|
#if ( XCHAL_CP_NUM > 0 && configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 )
|
|
/* Cleanup coproc save area */
|
|
vPortCleanUpCoprocArea( pxTCB );
|
|
#endif // ( XCHAL_CP_NUM > 0 && configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 )
|
|
}
|