Marius Vikhammer 57442c38bd core: fix cases where riscv SP were not 16 byte aligned ...

RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.

2021-06-02 16:02:10 +08:00

..

riscv

core: fix cases where riscv SP were not 16 byte aligned

2021-06-02 16:02:10 +08:00

xtensa

Merge branch 'bugfix/silent_asserts_v4.3' into 'release/v4.3'

2021-04-13 04:30:09 +00:00

port_common.c

freertos: Add RISC-V port

2020-11-13 07:49:11 +11:00