mirror of
https://github.com/espressif/esp-idf.git
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1f2cbde525
- Update the Key Manager key types to be generic - Define a new enum to determine the length of the keys - Refactor the Key Manager driver support generic key types and key lengths - Also store key deployment mode in the key recovery info
143 lines
4.7 KiB
C
143 lines
4.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_private/startup_internal.h"
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "esp_crypto_clk.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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#include "esp_security_priv.h"
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#include "esp_err.h"
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#include "hal/efuse_hal.h"
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#if SOC_HUK_MEM_NEEDS_RECHARGE
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#include "hal/huk_hal.h"
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#endif
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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#include "hal/key_mgr_ll.h"
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#include "hal/key_mgr_types.h"
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
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#include "hal/ecdsa_ll.h"
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#endif /* SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED */
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__attribute__((unused)) static const char *TAG = "esp_security";
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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static void esp_key_mgr_init(void)
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{
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// The following code initializes the key manager.
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// When Flash Encryption is already enabled, Key Manager is initialized by the
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// ROM, and when Flash Encryption is enabled during boot up, Key Manager is
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// initialized by the bootloader.
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if (!efuse_hal_flash_encryption_enabled()) {
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// Enable key manager clock
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key_mgr_ll_power_up();
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// Using ll APIs which do not require critical section
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_key_mgr_ll_enable_bus_clock(true);
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_key_mgr_ll_enable_peripheral_clock(true);
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_key_mgr_ll_reset_register();
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while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
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};
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// Force Key Manager to use eFuse key by-default for an XTS-AES operation.
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key_mgr_ll_set_key_usage(ESP_KEY_MGR_FLASH_XTS_AES_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
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}
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}
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
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{
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#if CONFIG_IDF_TARGET_ESP32C5
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// Check for unsupported configuration: flash encryption with CPU frequency > 160MHz
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// Manual encrypted flash writes are not stable at higher CPU clock.
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// Please refer to the ESP32-C5 SoC Errata document for more details.
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if (efuse_hal_flash_encryption_enabled() && CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ > 160) {
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ESP_EARLY_LOGE(TAG, "Flash encryption with CPU frequency > 160MHz is not supported. Please reconfigure the CPU frequency.");
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return ESP_ERR_NOT_SUPPORTED;
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}
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#endif
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esp_crypto_clk_init();
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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esp_key_mgr_init();
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#endif
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#if CONFIG_ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
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esp_crypto_dpa_protection_startup();
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#endif
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esp_err_t err = ESP_FAIL;
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#if CONFIG_ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL
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bool force_constant_time = true;
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#if CONFIG_IDF_TARGET_ESP32H2
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if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) {
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force_constant_time = false;
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}
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#endif
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if (!esp_efuse_read_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME) && force_constant_time) {
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ESP_EARLY_LOGD(TAG, "Forcefully enabling ECC constant time operations");
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err = esp_efuse_write_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME);
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if (err != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Enabling ECC constant time operations forcefully failed.");
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return err;
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}
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}
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#endif
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#if CONFIG_ESP_ECDSA_ENABLE_P192_CURVE
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err = esp_efuse_enable_ecdsa_p192_curve_mode();
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if (err != ESP_OK) {
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return err;
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}
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#endif
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#if CONFIG_SECURE_BOOT_V2_ENABLED
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// H2, H21
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#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
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// Also write protects the ECC_FORCE_CONST_TIME efuse bit.
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if (ecdsa_ll_is_configurable_curve_supported()) {
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err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to write protect the ECDSA_CURVE_MODE efuse bit.");
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return err;
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}
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}
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#endif
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#if !CONFIG_SECURE_BOOT_SKIP_WRITE_PROTECTION_SCA
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// C5
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#if SOC_ECDSA_SUPPORT_CURVE_P384 && !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS && !CONFIG_IDF_TARGET_ESP32P4
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// Since SECURE_BOOT_SHA384_EN, XTS_DPA_PSEUDO_LEVEL, and ECC_FORCE_CONST_TIME share the
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// same write-protection bit, these efuses should only be write-protected after all of
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// them have been programmed.
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// Note: ESP32-P4 lacks WR_DIS_SECURE_BOOT_SHA384_EN bit, so it relies on software protection
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// in the efuse write APIs (see esp_efuse_api.c) to prevent unauthorized programming of
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// SECURE_BOOT_SHA384_EN when Secure Boot using SHA-256 is enabled.
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err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to write protect the SECURE_BOOT_SHA384_EN efuse bit.");
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return err;
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}
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#endif
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#endif
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#endif
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err = ESP_OK;
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return err;
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}
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void esp_security_init_include_impl(void)
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{
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// Linker hook, exists for no other purpose
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}
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