mirror of
https://github.com/espressif/esp-idf.git
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89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
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* register description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
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/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
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#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
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#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
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#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
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/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
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* register description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
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/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
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#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
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#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
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#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
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/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
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* register description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
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/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
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#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
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#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
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#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
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/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
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* register description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
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/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
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#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
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#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
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#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
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/** INTPRI_DATE_REG register
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* register description
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*/
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#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
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/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
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* Need add description
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*/
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#define INTPRI_DATE 0x0FFFFFFFU
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#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
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#define INTPRI_DATE_V 0x0FFFFFFFU
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#define INTPRI_DATE_S 0
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/** INTPRI_CLOCK_GATE_REG register
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* register description
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*/
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#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
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/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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#define INTPRI_CLK_EN (BIT(0))
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#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
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#define INTPRI_CLK_EN_V 0x00000001U
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#define INTPRI_CLK_EN_S 0
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#ifdef __cplusplus
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}
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#endif
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