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https://github.com/espressif/esp-idf.git
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0a95151a75
There is no ccomp timer on C3, which means our performance tests will start failing again due to variance caused by cache misses. This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail performance test if CCOMP timer is supported on the target
422 lines
13 KiB
C
422 lines
13 KiB
C
#include <stdio.h>
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#include <sys/param.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <unity.h>
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#include <esp_spi_flash.h>
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#include <esp_attr.h>
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#include "driver/timer.h"
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#include "esp_intr_alloc.h"
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#include "test_utils.h"
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#include "ccomp_timer.h"
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "esp_timer.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/spi_flash.h"
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#endif
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struct flash_test_ctx {
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uint32_t offset;
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bool fail;
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SemaphoreHandle_t done;
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};
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static const char TAG[] = "test_spi_flash";
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/* Base offset in flash for tests. */
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static size_t start;
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static void setup_tests(void)
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{
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if (start == 0) {
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const esp_partition_t *part = get_test_data_partition();
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start = part->address;
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printf("Test data partition @ 0x%x\n", start);
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}
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}
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static void flash_test_task(void *arg)
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{
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struct flash_test_ctx *ctx = (struct flash_test_ctx *) arg;
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vTaskDelay(100 / portTICK_PERIOD_MS);
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const uint32_t sector = start / SPI_FLASH_SEC_SIZE + ctx->offset;
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printf("t%d\n", sector);
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printf("es%d\n", sector);
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if (spi_flash_erase_sector(sector) != ESP_OK) {
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ctx->fail = true;
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printf("Erase failed\r\n");
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xSemaphoreGive(ctx->done);
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vTaskDelete(NULL);
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}
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printf("ed%d\n", sector);
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vTaskDelay(0 / portTICK_PERIOD_MS);
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uint32_t val = 0xabcd1234;
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for (uint32_t offset = 0; offset < SPI_FLASH_SEC_SIZE; offset += 4) {
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if (spi_flash_write(sector * SPI_FLASH_SEC_SIZE + offset, (const uint8_t *) &val, 4) != ESP_OK) {
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printf("Write failed at offset=%d\r\n", offset);
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ctx->fail = true;
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break;
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}
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}
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printf("wd%d\n", sector);
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vTaskDelay(0 / portTICK_PERIOD_MS);
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uint32_t val_read;
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for (uint32_t offset = 0; offset < SPI_FLASH_SEC_SIZE; offset += 4) {
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if (spi_flash_read(sector * SPI_FLASH_SEC_SIZE + offset, (uint8_t *) &val_read, 4) != ESP_OK) {
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printf("Read failed at offset=%d\r\n", offset);
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ctx->fail = true;
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break;
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}
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if (val_read != val) {
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printf("Read invalid value=%08x at offset=%d\r\n", val_read, offset);
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ctx->fail = true;
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break;
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}
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}
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printf("td%d\n", sector);
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xSemaphoreGive(ctx->done);
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vTaskDelete(NULL);
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}
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TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_flash][ignore]")
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{
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setup_tests();
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SemaphoreHandle_t done = xSemaphoreCreateCounting(4, 0);
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struct flash_test_ctx ctx[] = {
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{ .offset = 0x10 + 6, .done = done },
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{ .offset = 0x10 + 7, .done = done },
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{ .offset = 0x10 + 8, .done = done },
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#ifndef CONFIG_FREERTOS_UNICORE
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{ .offset = 0x10 + 9, .done = done }
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#endif
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};
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xTaskCreatePinnedToCore(flash_test_task, "t0", 2048, &ctx[0], 3, NULL, 0);
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xTaskCreatePinnedToCore(flash_test_task, "t1", 2048, &ctx[1], 3, NULL, tskNO_AFFINITY);
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xTaskCreatePinnedToCore(flash_test_task, "t2", 2048, &ctx[2], 3, NULL, tskNO_AFFINITY);
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#ifndef CONFIG_FREERTOS_UNICORE
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xTaskCreatePinnedToCore(flash_test_task, "t3", 2048, &ctx[3], 3, NULL, 1);
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#endif
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const size_t task_count = sizeof(ctx)/sizeof(ctx[0]);
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for (int i = 0; i < task_count; ++i) {
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xSemaphoreTake(done, portMAX_DELAY);
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TEST_ASSERT_FALSE(ctx[i].fail);
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}
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vSemaphoreDelete(done);
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}
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typedef struct {
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size_t buf_size;
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uint8_t* buf;
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size_t flash_addr;
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size_t repeat_count;
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SemaphoreHandle_t done;
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} read_task_arg_t;
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typedef struct {
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size_t delay_time_us;
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size_t repeat_count;
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} block_task_arg_t;
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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#define int_clr_timers int_clr
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#endif
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static void IRAM_ATTR timer_isr(void* varg) {
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block_task_arg_t* arg = (block_task_arg_t*) varg;
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timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_0);
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timer_group_enable_alarm_in_isr(TIMER_GROUP_0, TIMER_0);
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esp_rom_delay_us(arg->delay_time_us);
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arg->repeat_count++;
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}
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static void read_task(void* varg) {
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read_task_arg_t* arg = (read_task_arg_t*) varg;
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for (size_t i = 0; i < arg->repeat_count; ++i) {
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ESP_ERROR_CHECK( spi_flash_read(arg->flash_addr, arg->buf, arg->buf_size) );
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}
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xSemaphoreGive(arg->done);
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vTaskDelay(1);
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vTaskDelete(NULL);
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}
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TEST_CASE("spi flash functions can run along with IRAM interrupts", "[spi_flash][esp_flash]")
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{
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const size_t size = 128;
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read_task_arg_t read_arg = {
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.buf_size = size,
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.buf = (uint8_t*) malloc(size),
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.flash_addr = 0,
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.repeat_count = 1000,
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.done = xSemaphoreCreateBinary()
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};
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timer_config_t config = {
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.alarm_en = true,
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.counter_en = false,
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.intr_type = TIMER_INTR_LEVEL,
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.counter_dir = TIMER_COUNT_UP,
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.auto_reload = true,
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.divider = 80
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};
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block_task_arg_t block_arg = {
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.repeat_count = 0,
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.delay_time_us = 100
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};
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ESP_ERROR_CHECK( timer_init(TIMER_GROUP_0, TIMER_0, &config) );
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timer_pause(TIMER_GROUP_0, TIMER_0);
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ESP_ERROR_CHECK( timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, 120) );
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intr_handle_t handle;
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ESP_ERROR_CHECK( timer_isr_register(TIMER_GROUP_0, TIMER_0, &timer_isr, &block_arg, ESP_INTR_FLAG_IRAM, &handle) );
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timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0);
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timer_enable_intr(TIMER_GROUP_0, TIMER_0);
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timer_start(TIMER_GROUP_0, TIMER_0);
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xTaskCreatePinnedToCore(read_task, "r", 2048, &read_arg, 3, NULL, portNUM_PROCESSORS - 1);
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xSemaphoreTake(read_arg.done, portMAX_DELAY);
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timer_pause(TIMER_GROUP_0, TIMER_0);
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timer_disable_intr(TIMER_GROUP_0, TIMER_0);
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esp_intr_free(handle);
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vSemaphoreDelete(read_arg.done);
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free(read_arg.buf);
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}
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typedef struct {
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uint32_t us_start;
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size_t len;
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const char* name;
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} time_meas_ctx_t;
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static void time_measure_start(time_meas_ctx_t* ctx)
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{
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ctx->us_start = esp_timer_get_time();
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ccomp_timer_start();
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}
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static uint32_t time_measure_end(time_meas_ctx_t* ctx)
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{
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uint32_t c_time_us = ccomp_timer_stop();
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uint32_t time_us = esp_timer_get_time() - ctx->us_start;
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ESP_LOGI(TAG, "%s: compensated: %.2lf kB/s, typical: %.2lf kB/s", ctx->name, ctx->len / (c_time_us/1000.), ctx->len / (time_us/1000.));
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return ctx->len * 1000 / (c_time_us / 1000);
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}
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#define TEST_TIMES 20
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#define TEST_SECTORS 4
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static uint32_t measure_erase(const esp_partition_t* part)
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{
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const int total_len = SPI_FLASH_SEC_SIZE * TEST_SECTORS;
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time_meas_ctx_t time_ctx = {.name = "erase", .len = total_len};
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time_measure_start(&time_ctx);
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esp_err_t err = spi_flash_erase_range(part->address, total_len);
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TEST_ESP_OK(err);
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return time_measure_end(&time_ctx);
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}
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// should called after measure_erase
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static uint32_t measure_write(const char* name, const esp_partition_t* part, const uint8_t* data_to_write, int seg_len)
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{
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const int total_len = SPI_FLASH_SEC_SIZE;
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time_meas_ctx_t time_ctx = {.name = name, .len = total_len * TEST_TIMES};
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time_measure_start(&time_ctx);
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for (int i = 0; i < TEST_TIMES; i ++) {
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// Erase one time, but write 100 times the same data
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size_t len = total_len;
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int offset = 0;
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while (len) {
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int len_write = MIN(seg_len, len);
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esp_err_t err = spi_flash_write(part->address + offset, data_to_write + offset, len_write);
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TEST_ESP_OK(err);
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offset += len_write;
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len -= len_write;
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}
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}
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return time_measure_end(&time_ctx);
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}
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static uint32_t measure_read(const char* name, const esp_partition_t* part, uint8_t* data_read, int seg_len)
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{
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const int total_len = SPI_FLASH_SEC_SIZE;
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time_meas_ctx_t time_ctx = {.name = name, .len = total_len * TEST_TIMES};
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time_measure_start(&time_ctx);
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for (int i = 0; i < TEST_TIMES; i ++) {
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size_t len = total_len;
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int offset = 0;
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while (len) {
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int len_read = MIN(seg_len, len);
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esp_err_t err = spi_flash_read(part->address + offset, data_read + offset, len_read);
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TEST_ESP_OK(err);
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offset += len_read;
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len -= len_read;
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}
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}
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return time_measure_end(&time_ctx);
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}
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#define MEAS_WRITE(n) (measure_write("write in "#n"-byte chunks", part, data_to_write, n))
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#define MEAS_READ(n) (measure_read("read in "#n"-byte chunks", part, data_read, n))
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TEST_CASE("Test spi_flash read/write performance", "[spi_flash]")
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{
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const esp_partition_t *part = get_test_data_partition();
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const int total_len = SPI_FLASH_SEC_SIZE;
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uint8_t *data_to_write = heap_caps_malloc(total_len, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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uint8_t *data_read = heap_caps_malloc(total_len, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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srand(777);
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for (int i = 0; i < total_len; i++) {
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data_to_write[i] = rand();
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}
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uint32_t erase_1 = measure_erase(part);
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uint32_t speed_WR_4B = MEAS_WRITE(4);
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uint32_t speed_RD_4B = MEAS_READ(4);
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uint32_t erase_2 = measure_erase(part);
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uint32_t speed_WR_2KB = MEAS_WRITE(2048);
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uint32_t speed_RD_2KB = MEAS_READ(2048);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(data_to_write, data_read, total_len);
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// Data checks are disabled when PSRAM is used or in Freertos compliance check test
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#if !CONFIG_SPIRAM && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
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# define CHECK_DATA(suffix) TEST_PERFORMANCE_CCOMP_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_LEGACY_##suffix, "%d", speed_##suffix)
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# define CHECK_ERASE(var) TEST_PERFORMANCE_CCOMP_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE, "%d", var)
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#else
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# define CHECK_DATA(suffix) ((void)speed_##suffix)
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# define CHECK_ERASE(var) ((void)var)
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#endif
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CHECK_DATA(WR_4B);
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CHECK_DATA(RD_4B);
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CHECK_DATA(WR_2KB);
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CHECK_DATA(RD_2KB);
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// Erase time may vary a lot, can increase threshold if this fails with a reasonable speed
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CHECK_ERASE(erase_1);
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CHECK_ERASE(erase_2);
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free(data_to_write);
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free(data_read);
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}
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#if portNUM_PROCESSORS > 1
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TEST_CASE("spi_flash deadlock with high priority busy-waiting task", "[spi_flash][esp_flash]")
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{
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typedef struct {
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QueueHandle_t queue;
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volatile bool done;
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} deadlock_test_arg_t;
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/* Create two tasks: high-priority consumer on CPU0, low-priority producer on CPU1.
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* Consumer polls the queue until it gets some data, then yields.
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* Run flash operation on CPU0. Check that when IPC1 task blocks out the producer,
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* the task which does flash operation does not get blocked by the consumer.
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*/
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void producer_task(void* varg)
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{
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int dummy = 0;
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deadlock_test_arg_t* arg = (deadlock_test_arg_t*) varg;
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while (!arg->done) {
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xQueueSend(arg->queue, &dummy, 0);
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vTaskDelay(1);
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}
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vTaskDelete(NULL);
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}
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void consumer_task(void* varg)
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{
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int dummy;
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deadlock_test_arg_t* arg = (deadlock_test_arg_t*) varg;
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while (!arg->done) {
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if (xQueueReceive(arg->queue, &dummy, 0) == pdTRUE) {
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vTaskDelay(1);
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}
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}
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vTaskDelete(NULL);
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}
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deadlock_test_arg_t arg = {
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.queue = xQueueCreate(32, sizeof(int)),
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.done = false
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};
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TEST_ASSERT(xTaskCreatePinnedToCore(&producer_task, "producer", 4096, &arg, 5, NULL, 1));
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TEST_ASSERT(xTaskCreatePinnedToCore(&consumer_task, "consumer", 4096, &arg, 10, NULL, 0));
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for (int i = 0; i < 1000; i++) {
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uint32_t dummy;
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TEST_ESP_OK(spi_flash_read(0, &dummy, sizeof(dummy)));
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}
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arg.done = true;
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vTaskDelay(5);
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vQueueDelete(arg.queue);
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/* Check that current task priority is still correct */
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TEST_ASSERT_EQUAL_INT(uxTaskPriorityGet(NULL), UNITY_FREERTOS_PRIORITY);
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}
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#endif // portNUM_PROCESSORS > 1
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TEST_CASE("WEL is cleared after boot", "[spi_flash]")
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{
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esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
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uint32_t status;
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esp_rom_spiflash_read_status(legacy_chip, &status);
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TEST_ASSERT((status & 0x2) == 0);
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}
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO
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// ISSI chip has its QE bit on other chips' BP4, which may get cleared by accident
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TEST_CASE("rom unlock will not erase QE bit", "[spi_flash]")
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{
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esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
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uint32_t status;
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printf("dev_id: %08X \n", legacy_chip->device_id);
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if (((legacy_chip->device_id >> 16) & 0xff) != 0x9D) {
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TEST_IGNORE_MESSAGE("This test is only for ISSI chips. Ignore.");
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}
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esp_rom_spiflash_unlock();
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esp_rom_spiflash_read_status(legacy_chip, &status);
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printf("status: %08x\n", status);
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TEST_ASSERT(status & 0x40);
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}
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#endif
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