Omar Chebib 5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer ...

G0 doesn't depend on any G1+ layer for RISC-V based targets

2022-06-14 15:00:53 +08:00

..

include/soc

G0: RISC-V targets have now an independent G0 layer

2022-06-14 15:00:53 +08:00

ld

soc: Adds efuse hal

2022-02-24 22:20:09 +08:00

adc_periph.c

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CMakeLists.txt

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dedic_gpio_periph.c

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gdma_periph.c

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gpio_periph.c

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i2c_bbpll.h

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i2c_periph.c

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i2s_periph.c

i2s: update copyright

2022-02-21 21:28:48 +08:00

interrupts.c

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ledc_periph.c

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rmt_periph.c

rmt: document and improve LL driver

2022-03-09 10:58:12 +08:00

sigmadelta_periph.c

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spi_periph.c

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timer_periph.c

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uart_periph.c

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