Files
esp-idf/components
Sachin Parekh 301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
2020-02-26 20:21:59 +08:00
..
2020-02-15 18:28:25 +08:00
2020-02-25 18:03:54 +08:00
2019-10-09 16:46:46 +08:00
2020-02-07 20:15:06 +08:00
2020-02-24 14:03:25 +08:00
2020-02-15 18:28:25 +08:00
2019-11-29 18:05:24 +08:00
2019-12-09 09:44:56 +08:00