mirror of
https://github.com/espressif/esp-idf.git
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07291fdd27
This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
135 lines
4.9 KiB
C
135 lines
4.9 KiB
C
// The long term plan is to have a single soc_caps.h for each peripheral.
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// During the refactoring and multichip support development process, we
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// seperate these information into periph_caps.h for each peripheral and
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// include them here.
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#pragma once
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#define SOC_CPU_CORES_NUM 1
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#define SOC_GDMA_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_DIG_SIGN_SUPPORTED 1
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#define SOC_HMAC_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#include "rmt_caps.h"
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/*-------------------------- DAC CAPS ----------------------------------------*/
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#define SOC_DAC_PERIPH_NUM 0
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#include "i2c_caps.h"
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#include "mpu_caps.h"
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#include "sigmadelta_caps.h"
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#include "systimer_caps.h"
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#include "uart_caps.h"
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#include "brownout_caps.h"
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#include "gdma_caps.h"
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#include "i2s_caps.h"
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#include "rtc_io_caps.h"
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#include "soc_caps.h"
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#include "timer_group_caps.h"
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#include "cpu_caps.h"
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#include "gpio_caps.h"
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#include "ledc_caps.h"
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#include "rmt_caps.h"
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#include "spi_caps.h"
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#include "uart_caps.h"
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#include "rtc_caps.h"
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
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#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
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/*-------------------------- TWAI CAPS ---------------------------------------*/
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#define SOC_TWAI_BRP_MIN 2
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#define SOC_TWAI_BRP_MAX 32768
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#define SOC_TWAI_SUPPORTS_RX_STATUS 1
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GDMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_AES_GDMA (1)
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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/*-------------------------- ADC CAPS -------------------------------*/
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_PATT_LEN_MAX (16)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
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#define SOC_ADC_MAX_CHANNEL_NUM (5)
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#define SOC_ADC_MAX_BITWIDTH (12)
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#define SOC_ADC_DIGI_FILTER_NUM (2)
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#define SOC_ADC_DIGI_MONITOR_NUM (2)
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#define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */
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#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
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//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (1)
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/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
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#define SOC_WIFI_HW_TSF (1)
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/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
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#define SOC_COEX_HW_PTI (1)
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/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
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/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
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#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
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/*-------------------------- SPI MEM CAPS ---------------------------------------*/
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#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
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#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
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#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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/*-------------------------- Power Management CAPS ----------------------------*/
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#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_CPU_PD (1)
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#define SOC_PM_SUPPORT_WIFI_PD (1)
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#define SOC_PM_SUPPORT_BT_PD (1)
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