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https://github.com/espressif/esp-idf.git
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83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "soc/syscon_reg.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "hal/adc_ll.h"
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#include "hal/adc_types.h"
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#include "hal/regi2c_ctrl_ll.h"
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#define ADC_RNG_CLKM_DIV_NUM 3
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#define ADC_RNG_CLKM_DIV_B 0
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#define ADC_RNG_CLKM_DIV_A 0
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void bootloader_random_enable(void)
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{
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SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_RNG_EN);
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// Enable 8M clock source for RNG (this is actually enough to produce strong random results,
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// but enabling the SAR ADC as well adds some insurance.)
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
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_adc_ll_reset_register();
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_adc_ll_enable_bus_clock(true);
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_adc_ll_enable_bus_clock(false);
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adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_APB);
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adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
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#ifndef BOOTLOADER_BUILD
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regi2c_saradc_enable();
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#else
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regi2c_ctrl_ll_i2c_sar_periph_enable();
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#endif
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// enable analog i2c master clock for RNG runtime
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ANALOG_CLOCK_ENABLE();
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adc_ll_regi2c_init();
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adc_digi_pattern_config_t pattern_config = {};
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pattern_config.unit = ADC_UNIT_1;
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pattern_config.atten = ADC_ATTEN_DB_12;
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pattern_config.channel = ADC_CHANNEL_10; //Use reserved channel to get internal voltage
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adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
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pattern_config.unit = ADC_UNIT_2;
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pattern_config.atten = ADC_ATTEN_DB_12;
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pattern_config.channel = ADC_CHANNEL_10; //Use reserved ADC2 and reserved channel to get internal voltage
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adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, 1);
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adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
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adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
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adc_ll_disable_sleep_controller();
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adc_ll_set_arbiter_work_mode(ADC_ARB_MODE_LOOP);
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adc_ll_digi_set_clk_div(3);
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adc_ll_digi_set_trigger_interval(70);
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adc_ll_digi_trigger_enable();
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}
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void bootloader_random_disable(void)
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{
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adc_ll_digi_trigger_disable();
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adc_ll_digi_reset_pattern_table();
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adc_ll_regi2c_adc_deinit();
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#ifndef BOOTLOADER_BUILD
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regi2c_saradc_disable();
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#endif
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// disable analog i2c master clock
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ANALOG_CLOCK_DISABLE();
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adc_ll_digi_controller_clk_div(4, 0, 0);
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adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_APB);
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adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
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}
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