mirror of
https://github.com/espressif/esp-idf.git
synced 2025-10-24 11:10:23 +00:00
76e606ab32
There was race condition where interrupt entries set by APP cpu core could have been cleared during PRO cpu startup. This was causing "cache access error" not being detected for ESP32 APP CPU core. This fix allows to NOT modify or clear any entries set by other core (APP or PRO) and thus avoiding any race conditions during startup code.
538 lines
18 KiB
C
538 lines
18 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_system.h"
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#include "esp_rom_uart.h"
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#include "esp_clk_internal.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_sys.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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#include "esp32/rtc.h"
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#include "esp32/cache_err_int.h"
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#include "esp32/rom/cache.h"
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#include "esp32/rom/rtc.h"
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#include "esp32/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rtc.h"
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#include "esp32s2/brownout.h"
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#include "esp32s2/cache_err_int.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/rtc.h"
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#include "esp32s2/spiram.h"
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#include "esp32s2/dport_access.h"
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#include "esp32s2/memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rtc.h"
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#include "esp32s3/brownout.h"
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#include "esp32s3/cache_err_int.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/rom/rtc.h"
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#include "esp32s3/spiram.h"
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#include "esp32s3/dport_access.h"
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#include "esp32s3/memprot.h"
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#include "soc/assist_debug_reg.h"
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#include "soc/cache_memory.h"
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#include "soc/system_reg.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rtc.h"
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#include "esp32c3/cache_err_int.h"
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/rtc.h"
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#include "soc/cache_memory.h"
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#include "esp32c3/memprot.h"
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#endif
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#include "bootloader_flash_config.h"
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#include "bootloader_flash.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_flash_encrypt.h"
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#include "hal/rtc_io_hal.h"
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#include "hal/gpio_hal.h"
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#include "hal/wdt_hal.h"
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#include "soc/rtc.h"
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#include "soc/efuse_reg.h"
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#include "soc/periph_defs.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/spinlock.h"
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#if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
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#include "trax.h"
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#endif
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#include "bootloader_mem.h"
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#if CONFIG_APP_BUILD_TYPE_ELF_RAM
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/spi_flash.h"
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#endif
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#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
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#include "esp_private/startup_internal.h"
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#include "esp_private/system_internal.h"
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extern int _bss_start;
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extern int _bss_end;
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extern int _rtc_bss_start;
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extern int _rtc_bss_end;
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extern int _vector_table;
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static const char *TAG = "cpu_start";
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern int _ext_ram_bss_start;
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extern int _ext_ram_bss_end;
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#endif
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#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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extern int _iram_bss_start;
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extern int _iram_bss_end;
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#endif
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
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static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
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static volatile bool s_resume_cores;
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#endif
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// If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
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bool g_spiram_ok = true;
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static void intr_matrix_clear(void)
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{
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uint32_t core_id = cpu_hal_get_core_id();
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for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
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intr_matrix_set(core_id, i, ETS_INVALID_INUM);
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}
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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void startup_resume_other_cores(void)
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{
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s_resume_cores = true;
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}
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void IRAM_ATTR call_start_cpu1(void)
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{
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cpu_hal_set_vecbase(&_vector_table);
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ets_set_appcpu_boot_addr(0);
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bootloader_init_mem();
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#if CONFIG_ESP_CONSOLE_UART_NONE
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esp_rom_install_channel_putc(1, NULL);
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esp_rom_install_channel_putc(2, NULL);
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#else // CONFIG_ESP_CONSOLE_UART_NONE
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esp_rom_install_uart_printf();
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esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
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#else
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REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
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REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
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#endif
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s_cpu_up[1] = true;
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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// Clear interrupt matrix for APP CPU core
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intr_matrix_clear();
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//Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
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//has started, but it isn't active *on this CPU* yet.
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esp_cache_err_int_init();
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_ESP32_TRAX_TWOBANKS
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trax_start_trace(TRAX_DOWNCOUNT_WORDS);
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#endif
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#endif
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s_cpu_inited[1] = true;
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while (!s_resume_cores) {
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esp_rom_delay_us(100);
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}
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SYS_STARTUP_FN();
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}
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static void start_other_core(void)
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{
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// If not the single core variant of ESP32 - check this since there is
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// no separate soc_caps.h for the single core variant.
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bool is_single_core = false;
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#if CONFIG_IDF_TARGET_ESP32
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is_single_core = REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU);
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#endif
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if (!is_single_core) {
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Flush(1);
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Cache_Read_Enable(1);
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#endif
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esp_cpu_unstall(1);
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// Enable clock and reset APP CPU. Note that OpenOCD may have already
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// enabled clock and taken APP CPU out of reset. In this case don't reset
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// APP CPU again, as that will clear the breakpoints which may have already
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// been set.
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#if CONFIG_IDF_TARGET_ESP32
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if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
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DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
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DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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}
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#elif CONFIG_IDF_TARGET_ESP32S3
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if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
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}
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#endif
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ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
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volatile bool cpus_up = false;
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while (!cpus_up) {
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cpus_up = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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cpus_up &= s_cpu_up[i];
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}
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esp_rom_delay_us(100);
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}
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}
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}
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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void IRAM_ATTR call_start_cpu0(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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RESET_REASON rst_reas[SOC_CPU_CORES_NUM];
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#else
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RESET_REASON rst_reas[1];
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#endif
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#ifdef __riscv
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// Configure the global pointer register
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// (This should be the first thing IDF app does, as any other piece of code could be
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// relaxed by the linker to access something relative to __global_pointer$)
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__asm__ __volatile__ (
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".option push\n"
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop"
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);
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#endif
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// Move exception vectors to IRAM
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cpu_hal_set_vecbase(&_vector_table);
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rst_reas[0] = rtc_get_reset_reason(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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rst_reas[1] = rtc_get_reset_reason(1);
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#endif
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#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
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// from panic handler we can be reset by RWDT or TG0WDT
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if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
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#endif
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) {
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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}
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#endif
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//Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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#if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
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// Clear IRAM BSS
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memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start));
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#endif
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/* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
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if (rst_reas[0] != DEEPSLEEP_RESET) {
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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/* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
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extern void esp_config_instruction_cache_mode(void);
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esp_config_instruction_cache_mode();
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/* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache.
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Configure the mode of data : cache size, cache associated ways, cache line size.
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Enable data cache, so if we don't use SPIRAM, it just works. */
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#if CONFIG_SPIRAM_BOOT_INIT
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extern void esp_config_data_cache_mode(void);
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esp_config_data_cache_mode();
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Cache_Enable_DCache(0);
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#endif
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#endif
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#if CONFIG_IDF_TARGET_ESP32S3
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/* Configure the mode of instruction cache : cache size, cache line size. */
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extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
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rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
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/* If we need use SPIRAM, we should use data cache.
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Configure the mode of data : cache size, cache line size.*/
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Cache_Suspend_DCache();
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extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
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rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
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Cache_Resume_DCache(0);
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#endif // CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
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extern int _rodata_reserved_start;
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uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
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uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
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Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
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bootloader_init_mem();
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#if CONFIG_SPIRAM_BOOT_INIT
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if (esp_spiram_init() != ESP_OK) {
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
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abort();
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#endif
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#endif
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
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g_spiram_ok = false;
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#else
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ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
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abort();
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#endif
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}
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if (g_spiram_ok) {
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esp_spiram_init_cache();
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}
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#endif
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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s_cpu_up[0] = true;
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#endif
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ESP_EARLY_LOGI(TAG, "Pro cpu up.");
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#if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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start_other_core();
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#else
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ESP_EARLY_LOGI(TAG, "Single core mode");
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#if CONFIG_IDF_TARGET_ESP32
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core
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#elif CONFIG_IDF_TARGET_ESP32S3
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
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#endif
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#endif // SOC_CPU_CORES_NUM > 1
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#if CONFIG_SPIRAM_MEMTEST
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if (g_spiram_ok) {
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bool ext_ram_ok = esp_spiram_test();
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if (!ext_ram_ok) {
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ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
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abort();
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}
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}
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#endif
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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extern void instruction_flash_page_info_init(void);
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instruction_flash_page_info_init();
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#endif
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#if CONFIG_SPIRAM_RODATA
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extern void rodata_flash_page_info_init(void);
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rodata_flash_page_info_init();
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#endif
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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extern void esp_spiram_enable_instruction_access(void);
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esp_spiram_enable_instruction_access();
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#endif
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#if CONFIG_SPIRAM_RODATA
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extern void esp_spiram_enable_rodata_access(void);
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esp_spiram_enable_rodata_access();
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#endif
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP
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uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP
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icache_wrap_enable = 1;
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#endif
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#if CONFIG_ESP32S2_DATA_CACHE_WRAP
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dcache_wrap_enable = 1;
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#endif
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extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
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esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
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#endif
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
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#endif
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//Enable trace memory and immediately start trace.
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#if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_ESP32_TRAX_TWOBANKS
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trax_enable(TRAX_ENA_PRO_APP);
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#else
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trax_enable(TRAX_ENA_PRO);
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#endif
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#elif CONFIG_IDF_TARGET_ESP32S2
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trax_enable(TRAX_ENA_PRO);
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#endif
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trax_start_trace(TRAX_DOWNCOUNT_WORDS);
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#endif // CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
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esp_clk_init();
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esp_perip_clk_init();
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// Now that the clocks have been set-up, set the startup time from RTC
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// and default RTC-backed system time provider.
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g_startup_time = esp_rtc_get_time_us();
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// Clear interrupt matrix for PRO CPU core
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intr_matrix_clear();
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|
|
|
#ifdef CONFIG_ESP_CONSOLE_UART
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uint32_t clock_hz = rtc_clk_apb_freq_get();
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|
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
|
|
clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
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#endif
|
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esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
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esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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#endif
|
|
|
|
#if SOC_RTCIO_HOLD_SUPPORTED
|
|
rtcio_hal_unhold_all();
|
|
#else
|
|
gpio_hal_force_unhold_all();
|
|
#endif
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|
|
|
esp_cache_err_int_init();
|
|
|
|
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
|
// Memprot cannot be locked during OS startup as the lock-on prevents any PMS changes until a next reboot
|
|
// If such a situation appears, it is likely an malicious attempt to bypass the system safety setup -> print error & reset
|
|
if ( esp_memprot_is_locked_any() ) {
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|
ESP_EARLY_LOGE(TAG, "Memprot feature locked after the system reset! Potential safety corruption, rebooting.");
|
|
esp_restart_noos_dig();
|
|
}
|
|
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
|
|
esp_memprot_set_prot(true, true, NULL);
|
|
#else
|
|
esp_memprot_set_prot(true, false, NULL);
|
|
#endif
|
|
#endif
|
|
|
|
bootloader_flash_update_id();
|
|
// Read the application binary image header. This will also decrypt the header if the image is encrypted.
|
|
__attribute__((unused)) esp_image_header_t fhdr = {0};
|
|
#ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM
|
|
fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO;
|
|
fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_40M;
|
|
fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB;
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|
|
|
extern void esp_rom_spiflash_attach(uint32_t, bool);
|
|
esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
|
|
bootloader_flash_unlock();
|
|
#else
|
|
// This assumes that DROM is the first segment in the application binary, i.e. that we can read
|
|
// the binary header through cache by accessing SOC_DROM_LOW address.
|
|
memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr));
|
|
#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
#if !CONFIG_SPIRAM_BOOT_INIT
|
|
// If psram is uninitialized, we need to improve some flash configuration.
|
|
bootloader_flash_clock_config(&fhdr);
|
|
bootloader_flash_gpio_config(&fhdr);
|
|
bootloader_flash_dummy_config(&fhdr);
|
|
bootloader_flash_cs_timing_config();
|
|
#endif //!CONFIG_SPIRAM_BOOT_INIT
|
|
#endif //CONFIG_IDF_TARGET_ESP32
|
|
|
|
#if CONFIG_SPI_FLASH_SIZE_OVERRIDE
|
|
int app_flash_size = esp_image_get_flash_size(fhdr.spi_size);
|
|
if (app_flash_size < 1 * 1024 * 1024) {
|
|
ESP_LOGE(TAG, "Invalid flash size in app image header.");
|
|
abort();
|
|
}
|
|
bootloader_flash_update_size(app_flash_size);
|
|
#endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE
|
|
|
|
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
s_cpu_inited[0] = true;
|
|
|
|
volatile bool cpus_inited = false;
|
|
|
|
while (!cpus_inited) {
|
|
cpus_inited = true;
|
|
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
|
|
cpus_inited &= s_cpu_inited[i];
|
|
}
|
|
esp_rom_delay_us(100);
|
|
}
|
|
#endif
|
|
|
|
SYS_STARTUP_FN();
|
|
}
|