Jiang Jiang Jian b2bc2dfcc3 Merge branch 'bugfix/riscv_task_wdt_cleanup_v5.3' into 'release/v5.3' ...

fix(wdt): changed register dump on task WDT to be more descriptive (v5.3)

See merge request espressif/esp-idf!33105

2024-10-17 10:39:56 +08:00

..

include

Merge branch 'bugfix/riscv_task_wdt_cleanup_v5.3' into 'release/v5.3'

2024-10-17 10:39:56 +08:00

ld

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

CMakeLists.txt

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

instruction_decode.c

refactor(tools): Tidy up core component files copyright ignore

2024-01-22 18:07:35 +08:00

interrupt_clic.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt_intc.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt_plic.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt.c

feat(esp32c61): add G0 component support

2024-03-18 14:28:27 +08:00

linker.lf

riscv: moved some interrupt functions from IRAM to flash

2023-04-10 12:21:11 +08:00

project_include.cmake

…

vectors_clic.S

feat(system): esp32p4: support hw stack guard

2024-03-21 14:30:21 +04:00

vectors_intc.S

fix: mark .exception_vectors* as executable and allocatable

2024-03-21 08:53:09 +01:00

vectors.S

fix(riscv): make HWLP feature use direct saving of lazy saving

2024-05-22 16:58:31 +08:00