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https://github.com/espressif/esp-idf.git
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872c42ecf7
* Issue: https://github.com/espressif/esp-idf/issues/7082 Signed-off-by: Yuriy Shestakov <yshestakov@gmail.com> Closes https://github.com/espressif/esp-idf/issues/7082 Closes https://github.com/espressif/esp-idf/pull/7441
336 lines
10 KiB
C
336 lines
10 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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#include "soc/efuse_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "soc/assist_debug_reg.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/spi_periph.h"
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#include "soc/extmem_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/system_reg.h"
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#include "esp32c3/rom/efuse.h"
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#include "esp32c3/rom/spi_flash.h"
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/ets_sys.h"
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#include "esp32c3/rom/spi_flash.h"
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#include "esp32c3/rom/rtc.h"
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#include "bootloader_common.h"
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#include "bootloader_init.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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#include "regi2c_ctrl.h"
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#include "bootloader_console.h"
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#include "bootloader_flash_priv.h"
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static const char *TAG = "boot.esp32c3";
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
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uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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if (spiconfig == 0) {
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} else {
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clk_gpio_num = spiconfig & 0x3f;
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q_gpio_num = (spiconfig >> 6) & 0x3f;
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d_gpio_num = (spiconfig >> 12) & 0x3f;
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cs0_gpio_num = (spiconfig >> 18) & 0x3f;
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hd_gpio_num = (spiconfig >> 24) & 0x3f;
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wp_gpio_num = wp_pin;
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}
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esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
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if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
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}
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if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
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}
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}
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static void bootloader_reset_mmu(void)
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{
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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}
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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}
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uint32_t autoload = Cache_Suspend_ICache();
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// Set flash chip size
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esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
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Cache_Resume_ICache(autoload);
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}
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static void print_flash_info(const esp_image_header_t *bootloader_hdr)
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{
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ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
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ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
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ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
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ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
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ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
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const char *str;
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switch (bootloader_hdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_40M:
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str = "40MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_26M:
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str = "26.7MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_20M:
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str = "20MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_80M:
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str = "80MHz";
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break;
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default:
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str = "20MHz";
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break;
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}
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ESP_LOGI(TAG, "SPI Speed : %s", str);
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/* SPI mode could have been set to QIO during boot already,
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so test the SPI registers not the flash header */
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uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
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if (spi_ctrl & SPI_MEM_FREAD_QIO) {
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str = "QIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
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str = "QOUT";
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} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
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str = "DIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
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str = "DOUT";
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} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
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str = "FAST READ";
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} else {
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str = "SLOW READ";
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}
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ESP_LOGI(TAG, "SPI Mode : %s", str);
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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str = "1MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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str = "2MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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str = "4MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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str = "8MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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str = "16MB";
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break;
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default:
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str = "2MB";
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break;
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}
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ESP_LOGI(TAG, "SPI Flash Size : %s", str);
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}
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static void IRAM_ATTR bootloader_init_flash_configure(void)
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{
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bootloader_flash_dummy_config(&bootloader_image_hdr);
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bootloader_flash_cs_timing_config();
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}
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static void bootloader_spi_flash_resume(void)
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{
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bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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}
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static esp_err_t bootloader_init_spi_flash(void)
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{
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bootloader_init_flash_configure();
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#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
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ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
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return ESP_FAIL;
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}
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#endif
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bootloader_spi_flash_resume();
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esp_rom_spiflash_unlock();
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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bootloader_enable_qio_mode();
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#endif
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print_flash_info(&bootloader_image_hdr);
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update_flash_config(&bootloader_image_hdr);
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//ensure the flash is write-protected
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bootloader_enable_wp();
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return ESP_OK;
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}
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static void wdt_reset_cpu0_info_enable(void)
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{
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REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
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REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
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}
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static void wdt_reset_info_dump(int cpu)
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{
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// TODO ESP32-C3 IDF-2118
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ESP_LOGE(TAG, "WDT reset info dump is not supported yet");
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}
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static void bootloader_check_wdt_reset(void)
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{
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int wdt_rst = 0;
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RESET_REASON rst_reas[2];
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rst_reas[0] = rtc_get_reset_reason(0);
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if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
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rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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}
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wdt_reset_cpu0_info_enable();
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}
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
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REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
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}
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static inline void bootloader_hardware_init(void)
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{
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// This check is always included in the bootloader so it can
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// print the minimum revision error message later in the boot
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if (bootloader_common_get_chip_revision() < 3) {
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
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REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
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}
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}
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static inline void bootloader_glitch_reset_disable(void)
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{
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/*
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For origin chip & ECO1: only support swt reset;
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For ECO2: fix brownout reset bug, support swt & brownout reset;
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For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
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*/
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uint8_t chip_version = bootloader_common_get_chip_revision();
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if (chip_version < 2) {
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REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
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} else {
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// checked on ESP32-C3 revisions 2 and 3
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REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
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}
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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bootloader_hardware_init();
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bootloader_glitch_reset_disable();
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bootloader_super_wdt_auto_feed();
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// protect memory region
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bootloader_init_mem();
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/* check that static RAM is after the stack */
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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// clear bss section
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bootloader_clear_bss_section();
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// reset MMU
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bootloader_reset_mmu();
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// config clock
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bootloader_clock_configure();
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// initialize console, from now on, we can use esp_log
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bootloader_console_init();
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/* print 2nd bootloader banner */
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bootloader_print_banner();
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// update flash ID
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bootloader_flash_update_id();
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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goto err;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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goto err;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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goto err;
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}
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// check whether a WDT reset happend
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bootloader_check_wdt_reset();
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// config WDT
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bootloader_config_wdt();
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// enable RNG early entropy source
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bootloader_enable_random();
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err:
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return ret;
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}
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