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			94 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			94 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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|  *
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|  * SPDX-License-Identifier: Apache-2.0
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|  */
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| 
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| #include <stdint.h>
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| #include "esp_cpu.h"
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| #include "soc/soc.h"
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| #include "soc/soc_caps.h"
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| #include "esp_private/rtc_clk.h"
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| #include "esp_private/panic_internal.h"
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| #include "esp_private/system_internal.h"
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| #include "esp_private/mspi_timing_tuning.h"
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| #include "esp_heap_caps.h"
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| #include "esp_rom_uart.h"
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| #include "esp_rom_sys.h"
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| #include "sdkconfig.h"
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| 
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| // used only by ESP32 panic handler
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| #ifdef CONFIG_IDF_TARGET_ESP32
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| void IRAM_ATTR esp_restart_noos_dig(void)
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| {
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|     // In case any of the calls below results in re-enabling of interrupts
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|     // (for example, by entering a critical section), disable all the
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|     // interrupts (e.g. from watchdogs) here.
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| #ifdef CONFIG_IDF_TARGET_ARCH_RISCV
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|     rv_utils_intr_global_disable();
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| #else
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|     xt_ints_off(0xFFFFFFFF);
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| #endif
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| 
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|     if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM != -1) {
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|         esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
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|     }
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| 
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| #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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|     /**
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|      * Turn down MSPI speed
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|      *
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|      * We set MSPI clock to a high speed one before, ROM doesn't have such high speed clock source option.
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|      * This function will change clock source to a ROM supported one when system restarts.
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|      */
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|     mspi_timing_change_speed_mode_cache_safe(true);
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| #endif  //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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| 
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|     // switch to XTAL (otherwise we will keep running from the PLL)
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|     rtc_clk_cpu_set_to_default_config();
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| 
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|     // esp_restart_noos_dig() will generates a core reset, which does not reset the
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|     // registers of the RTC domain, so the CPU's stall state remains after the reset,
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|     // we need to release them here
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| #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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|     // unstall all other cores
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|     int core_id = esp_cpu_get_core_id();
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|     for (uint32_t i = 0; i < SOC_CPU_CORES_NUM; i++) {
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|         if (i != core_id) {
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|             esp_cpu_unstall(i);
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|         }
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|     }
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| #endif
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|     // generate core reset
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|     esp_rom_software_reset_system();
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|     while (true) {
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|         ;
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|     }
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| }
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| #endif
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| 
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| uint32_t esp_get_free_heap_size(void)
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| {
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|     return heap_caps_get_free_size(MALLOC_CAP_DEFAULT);
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| }
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| 
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| uint32_t esp_get_free_internal_heap_size(void)
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| {
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|     return heap_caps_get_free_size(MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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| }
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| 
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| uint32_t esp_get_minimum_free_heap_size(void)
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| {
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|     return heap_caps_get_minimum_free_size(MALLOC_CAP_DEFAULT);
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| }
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| 
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| const char *esp_get_idf_version(void)
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| {
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|     return IDF_VER;
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| }
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| 
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| void __attribute__((noreturn)) esp_system_abort(const char *details)
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| {
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|     panic_abort(details);
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| }
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