mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-28 21:33:32 +00:00

In some cases, when data was just written into UART FIFO, transmitter state could be still zero while the FIFO did contain some data. This resulted in uart_tx_wait_idle occasionally returning before all the data was sent out. Fix by checking both UART transmitter state and TX FIFO count.