mirror of
https://github.com/espressif/esp-idf.git
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230 lines
8.5 KiB
C
230 lines
8.5 KiB
C
/**
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** GPIO_SD_SIGMADELTA0_REG register
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* Duty Cycle Configure Register of SDM0
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*/
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#define GPIO_SD_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
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/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
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* This field is used to configure the duty cycle of sigma delta modulation output.
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*/
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#define GPIO_SD_SD0_IN 0x000000FFU
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#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
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#define GPIO_SD_SD0_IN_V 0x000000FFU
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#define GPIO_SD_SD0_IN_S 0
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/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
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* This field is used to set a divider value to divide APB clock.
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*/
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#define GPIO_SD_SD0_PRESCALE 0x000000FFU
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#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
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#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU
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#define GPIO_SD_SD0_PRESCALE_S 8
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/** GPIO_SD_SIGMADELTA1_REG register
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* Duty Cycle Configure Register of SDM1
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*/
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#define GPIO_SD_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
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/** GPIO_SD_SD1_IN : R/W; bitpos: [7:0]; default: 0;
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* This field is used to configure the duty cycle of sigma delta modulation output.
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*/
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#define GPIO_SD_SD1_IN 0x000000FFU
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#define GPIO_SD_SD1_IN_M (GPIO_SD_SD1_IN_V << GPIO_SD_SD1_IN_S)
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#define GPIO_SD_SD1_IN_V 0x000000FFU
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#define GPIO_SD_SD1_IN_S 0
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/** GPIO_SD_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
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* This field is used to set a divider value to divide APB clock.
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*/
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#define GPIO_SD_SD1_PRESCALE 0x000000FFU
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#define GPIO_SD_SD1_PRESCALE_M (GPIO_SD_SD1_PRESCALE_V << GPIO_SD_SD1_PRESCALE_S)
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#define GPIO_SD_SD1_PRESCALE_V 0x000000FFU
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#define GPIO_SD_SD1_PRESCALE_S 8
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/** GPIO_SD_SIGMADELTA2_REG register
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* Duty Cycle Configure Register of SDM2
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*/
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#define GPIO_SD_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
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/** GPIO_SD_SD2_IN : R/W; bitpos: [7:0]; default: 0;
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* This field is used to configure the duty cycle of sigma delta modulation output.
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*/
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#define GPIO_SD_SD2_IN 0x000000FFU
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#define GPIO_SD_SD2_IN_M (GPIO_SD_SD2_IN_V << GPIO_SD_SD2_IN_S)
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#define GPIO_SD_SD2_IN_V 0x000000FFU
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#define GPIO_SD_SD2_IN_S 0
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/** GPIO_SD_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
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* This field is used to set a divider value to divide APB clock.
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*/
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#define GPIO_SD_SD2_PRESCALE 0x000000FFU
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#define GPIO_SD_SD2_PRESCALE_M (GPIO_SD_SD2_PRESCALE_V << GPIO_SD_SD2_PRESCALE_S)
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#define GPIO_SD_SD2_PRESCALE_V 0x000000FFU
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#define GPIO_SD_SD2_PRESCALE_S 8
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/** GPIO_SD_SIGMADELTA3_REG register
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* Duty Cycle Configure Register of SDM3
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*/
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#define GPIO_SD_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xc)
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/** GPIO_SD_SD3_IN : R/W; bitpos: [7:0]; default: 0;
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* This field is used to configure the duty cycle of sigma delta modulation output.
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*/
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#define GPIO_SD_SD3_IN 0x000000FFU
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#define GPIO_SD_SD3_IN_M (GPIO_SD_SD3_IN_V << GPIO_SD_SD3_IN_S)
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#define GPIO_SD_SD3_IN_V 0x000000FFU
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#define GPIO_SD_SD3_IN_S 0
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/** GPIO_SD_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
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* This field is used to set a divider value to divide APB clock.
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*/
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#define GPIO_SD_SD3_PRESCALE 0x000000FFU
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#define GPIO_SD_SD3_PRESCALE_M (GPIO_SD_SD3_PRESCALE_V << GPIO_SD_SD3_PRESCALE_S)
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#define GPIO_SD_SD3_PRESCALE_V 0x000000FFU
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#define GPIO_SD_SD3_PRESCALE_S 8
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/** GPIO_SD_SIGMADELTA_CG_REG register
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* Clock Gating Configure Register
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*/
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#define GPIO_SD_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
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/** GPIO_SD_CLK_EN : R/W; bitpos: [31]; default: 0;
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* Clock enable bit of configuration registers for sigma delta modulation.
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*/
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#define GPIO_SD_CLK_EN (BIT(31))
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#define GPIO_SD_CLK_EN_M (GPIO_SD_CLK_EN_V << GPIO_SD_CLK_EN_S)
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#define GPIO_SD_CLK_EN_V 0x00000001U
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#define GPIO_SD_CLK_EN_S 31
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/** GPIO_SD_SIGMADELTA_MISC_REG register
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* MISC Register
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*/
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#define GPIO_SD_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
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/** GPIO_SD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
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* Clock enable bit of sigma delta modulation.
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*/
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#define GPIO_SD_FUNCTION_CLK_EN (BIT(30))
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#define GPIO_SD_FUNCTION_CLK_EN_M (GPIO_SD_FUNCTION_CLK_EN_V << GPIO_SD_FUNCTION_CLK_EN_S)
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#define GPIO_SD_FUNCTION_CLK_EN_V 0x00000001U
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#define GPIO_SD_FUNCTION_CLK_EN_S 30
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/** GPIO_SD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
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* Reserved.
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*/
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#define GPIO_SD_SPI_SWAP (BIT(31))
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#define GPIO_SD_SPI_SWAP_M (GPIO_SD_SPI_SWAP_V << GPIO_SD_SPI_SWAP_S)
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#define GPIO_SD_SPI_SWAP_V 0x00000001U
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#define GPIO_SD_SPI_SWAP_S 31
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/** GPIO_SD_PAD_COMP_CONFIG_REG register
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* PAD Compare configure Register
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*/
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#define GPIO_SD_PAD_COMP_CONFIG_REG (DR_REG_GPIO_SD_BASE + 0x28)
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/** GPIO_SD_XPD_COMP : R/W; bitpos: [0]; default: 0;
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* Pad compare enable bit.
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*/
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#define GPIO_SD_XPD_COMP (BIT(0))
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#define GPIO_SD_XPD_COMP_M (GPIO_SD_XPD_COMP_V << GPIO_SD_XPD_COMP_S)
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#define GPIO_SD_XPD_COMP_V 0x00000001U
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#define GPIO_SD_XPD_COMP_S 0
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/** GPIO_SD_MODE_COMP : R/W; bitpos: [1]; default: 0;
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* 1 to enable external reference from PAD[0]. 0 to enable internal reference,
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* meanwhile PAD[0] can be used as a regular GPIO.
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*/
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#define GPIO_SD_MODE_COMP (BIT(1))
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#define GPIO_SD_MODE_COMP_M (GPIO_SD_MODE_COMP_V << GPIO_SD_MODE_COMP_S)
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#define GPIO_SD_MODE_COMP_V 0x00000001U
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#define GPIO_SD_MODE_COMP_S 1
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/** GPIO_SD_DREF_COMP : R/W; bitpos: [4:2]; default: 0;
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* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
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*/
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#define GPIO_SD_DREF_COMP 0x00000007U
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#define GPIO_SD_DREF_COMP_M (GPIO_SD_DREF_COMP_V << GPIO_SD_DREF_COMP_S)
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#define GPIO_SD_DREF_COMP_V 0x00000007U
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#define GPIO_SD_DREF_COMP_S 2
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/** GPIO_SD_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0;
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* Zero Detect mode select.
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*/
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#define GPIO_SD_ZERO_DET_MODE 0x00000003U
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#define GPIO_SD_ZERO_DET_MODE_M (GPIO_SD_ZERO_DET_MODE_V << GPIO_SD_ZERO_DET_MODE_S)
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#define GPIO_SD_ZERO_DET_MODE_V 0x00000003U
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#define GPIO_SD_ZERO_DET_MODE_S 5
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/** GPIO_SD_PAD_COMP_FILTER_REG register
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* Zero Detect filter Register
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*/
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#define GPIO_SD_PAD_COMP_FILTER_REG (DR_REG_GPIO_SD_BASE + 0x2c)
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/** GPIO_SD_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0;
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* Zero Detect filter cycle length
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*/
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#define GPIO_SD_ZERO_DET_FILTER_CNT 0xFFFFFFFFU
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#define GPIO_SD_ZERO_DET_FILTER_CNT_M (GPIO_SD_ZERO_DET_FILTER_CNT_V << GPIO_SD_ZERO_DET_FILTER_CNT_S)
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#define GPIO_SD_ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU
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#define GPIO_SD_ZERO_DET_FILTER_CNT_S 0
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/** GPIO_SD_INT_RAW_REG register
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* GPIO_SD interrupt raw register
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*/
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#define GPIO_SD_INT_RAW_REG (DR_REG_GPIO_SD_BASE + 0x80)
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/** GPIO_SD_PAD_COMP_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* Pad compare raw interrupt
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*/
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#define GPIO_SD_PAD_COMP_INT_RAW (BIT(0))
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#define GPIO_SD_PAD_COMP_INT_RAW_M (GPIO_SD_PAD_COMP_INT_RAW_V << GPIO_SD_PAD_COMP_INT_RAW_S)
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#define GPIO_SD_PAD_COMP_INT_RAW_V 0x00000001U
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#define GPIO_SD_PAD_COMP_INT_RAW_S 0
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/** GPIO_SD_INT_ST_REG register
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* GPIO_SD interrupt masked register
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*/
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#define GPIO_SD_INT_ST_REG (DR_REG_GPIO_SD_BASE + 0x84)
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/** GPIO_SD_PAD_COMP_INT_ST : RO; bitpos: [0]; default: 0;
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* Pad compare masked interrupt
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*/
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#define GPIO_SD_PAD_COMP_INT_ST (BIT(0))
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#define GPIO_SD_PAD_COMP_INT_ST_M (GPIO_SD_PAD_COMP_INT_ST_V << GPIO_SD_PAD_COMP_INT_ST_S)
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#define GPIO_SD_PAD_COMP_INT_ST_V 0x00000001U
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#define GPIO_SD_PAD_COMP_INT_ST_S 0
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/** GPIO_SD_INT_ENA_REG register
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* GPIO_SD interrupt enable register
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*/
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#define GPIO_SD_INT_ENA_REG (DR_REG_GPIO_SD_BASE + 0x88)
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/** GPIO_SD_PAD_COMP_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Pad compare interrupt enable
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*/
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#define GPIO_SD_PAD_COMP_INT_ENA (BIT(0))
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#define GPIO_SD_PAD_COMP_INT_ENA_M (GPIO_SD_PAD_COMP_INT_ENA_V << GPIO_SD_PAD_COMP_INT_ENA_S)
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#define GPIO_SD_PAD_COMP_INT_ENA_V 0x00000001U
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#define GPIO_SD_PAD_COMP_INT_ENA_S 0
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/** GPIO_SD_INT_CLR_REG register
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* GPIO_SD interrupt clear register
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*/
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#define GPIO_SD_INT_CLR_REG (DR_REG_GPIO_SD_BASE + 0x8c)
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/** GPIO_SD_PAD_COMP_INT_CLR : WT; bitpos: [0]; default: 0;
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* Pad compare interrupt clear
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*/
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#define GPIO_SD_PAD_COMP_INT_CLR (BIT(0))
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#define GPIO_SD_PAD_COMP_INT_CLR_M (GPIO_SD_PAD_COMP_INT_CLR_V << GPIO_SD_PAD_COMP_INT_CLR_S)
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#define GPIO_SD_PAD_COMP_INT_CLR_V 0x00000001U
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#define GPIO_SD_PAD_COMP_INT_CLR_S 0
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/** GPIO_SD_SIGMADELTA_VERSION_REG register
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* Version Control Register
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*/
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#define GPIO_SD_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0xfc)
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/** GPIO_SD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 34668848;
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* Version control register.
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*/
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#define GPIO_SD_GPIO_SD_DATE 0x0FFFFFFFU
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#define GPIO_SD_GPIO_SD_DATE_M (GPIO_SD_GPIO_SD_DATE_V << GPIO_SD_GPIO_SD_DATE_S)
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#define GPIO_SD_GPIO_SD_DATE_V 0x0FFFFFFFU
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#define GPIO_SD_GPIO_SD_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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