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85 lines
2.0 KiB
C
85 lines
2.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* Background
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*
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* This file is for the MSPI related, but not Flash driver related registers, these registers:
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* - may influence both Flash and PSRAM
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* - not related or directly related to Flash controller driver
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*
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* Some hints for naming convention:
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* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
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* - For others, the LL should start with `mspi_ll_`
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/pcr_struct.h"
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#include "hal/misc.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/************************** MSPI pll clock configurations **************************/
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/*
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* @brief Select FLASH clock source
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*
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* @param mspi_id mspi_id
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* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
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*/
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__attribute__((always_inline))
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static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
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{
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HAL_ASSERT(mspi_id == 0);
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switch (clk_src) {
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case FLASH_CLK_SRC_XTAL:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
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break;
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case FLASH_CLK_SRC_RC_FAST:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
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break;
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case FLASH_CLK_SRC_SPLL:
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PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
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break;
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default:
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HAL_ASSERT(false);
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}
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}
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/**
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* @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
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*
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* @param divider Divider.
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*/
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static inline __attribute__((always_inline)) void mspi_ll_fast_set_hs_divider(uint32_t divider)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
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}
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/**
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* @brief Enable the mspi bus clock
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*
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* @param enable enable the bus clock
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*/
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static inline __attribute__((always_inline)) void mspi_ll_enable_bus_clock(bool enable)
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{
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PCR.mspi_conf.mspi_clk_en = enable;
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}
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#ifdef __cplusplus
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}
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#endif
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