Jiang Jiang Jian f409428bf3 Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0' ...

fix(spi_flash): Add CPU frequency switching during flash encrypted write (v6.0)

See merge request espressif/esp-idf!44304

2025-12-21 15:28:33 +08:00

..

arch

refactor: avoid function calls inside MIN/MAX macros

2025-11-18 15:18:14 +08:00

include

fix(esp_system): clear cache error interrupt in panic handler

2025-09-24 21:30:56 +07:00

soc

Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"

2025-12-17 01:21:46 +08:00

CMakeLists.txt

fix(clk): 400MHz CPU should still be selectable on ESP32-P4 less than rev3

2025-11-12 22:28:03 +08:00

cpu_start.c

fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore

2025-12-15 14:47:54 +01:00

esp_ipc_isr.c

feat(esp_system): Adds Kconfigs to place code in IRAM

2025-06-23 13:23:33 +03:00

esp_system_chip.c

refactor(uart)!: deprcated esp_rom_uart.h

2025-07-08 18:56:17 +08:00

esp_system_linux.c

refactor(system): removed esp_system from astyle ignore list and reformated it

2024-01-30 15:17:15 +08:00

image_process.c

feat(psram): xip psram c5

2024-09-03 18:17:03 +08:00

panic_handler.c

remove(esp_hw_support): Remove redundant and unsupported memprot mentions

2025-08-04 11:43:01 +05:30