Guillaume Souchere 6dffac74e9 heap: Fix IRAM level 2 starting address ...

The IRAM level 2 address should start at the same address as DRAM level 2 and not DRAM level 3.

2023-01-06 09:30:36 +00:00

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esp32

heap: adjust the order of RTC memory heap caps and regions

2021-12-29 08:49:42 +00:00

esp32c2

use enum and designated initializers in soc_memory_type define

2022-07-29 17:07:41 +08:00

esp32c3

use enum and designated initializers in soc_memory_type define

2022-07-29 17:07:41 +08:00

esp32c6

heap: Fix IRAM level 2 starting address

2023-01-06 09:30:36 +00:00

esp32h2

esp32h2 memory: update esp32h2 memory layout

2023-01-06 05:30:24 +00:00

esp32h4

esp32h2: renaming esp32h2 to esp32h4

2022-11-08 17:05:33 +08:00

esp32s2

heap: adjust the order of RTC memory heap caps and regions

2021-12-29 08:49:42 +00:00

esp32s3

bugfix: DCache data memory is dma accessible but not retention dma accessible

2022-08-03 20:07:39 +08:00

memory_layout_utils.c

ESP32H2: Introduce new chip target esp32h2, hello_world example supported

2022-12-29 12:29:14 +08:00