Chen Jichang 62700fa36f feat(esp32h4): add soc register header files (stage2_3) ...

add soc headers made by hand

2025-02-24 12:20:27 +08:00

..

include

feat(esp32h4): add soc register header files (stage2_3)

2025-02-24 12:20:27 +08:00

ld

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

CMakeLists.txt

feat(esp_tee): Support for ESP-TEE - riscv component

2024-12-02 12:20:04 +05:30

instruction_decode.c

refactor(tools): Tidy up core component files copyright ignore

2024-01-22 18:07:35 +08:00

interrupt_clic.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt_intc.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt_plic.c

refactor(esp_tee): Revised the secure service ID numbering scheme

2025-01-23 12:39:19 +05:30

interrupt.c

feat(intr): basic interrupt/freertos support for C61

2024-06-12 09:25:47 +08:00

linker.lf

riscv: moved some interrupt functions from IRAM to flash

2023-04-10 12:21:11 +08:00

project_include.cmake

build: Adds support for universal Clang toolchain

2022-11-23 13:25:16 +03:00

vectors_clic.S

feat(system): esp32p4: support hw stack guard

2024-03-21 14:30:21 +04:00

vectors_intc.S

fix: mark .exception_vectors* as executable and allocatable

2024-03-21 08:53:09 +01:00

vectors.S

feat(esp_tee): Support for ESP-TEE - riscv component

2024-12-02 12:20:04 +05:30