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a0c91ea08287cde1efe57cb3b56cbdde34bdff25
esp-idf/components/riscv
History
Alexey Lapshin ad7f4b9670 feat(esp_libc): make picolibc default libc
2025-12-06 00:08:35 +07:00
..
include
feat(esp_libc): make picolibc default libc
2025-12-06 00:08:35 +07:00
ld
…
CMakeLists.txt
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-08-13 14:08:59 +05:30
instruction_decode.c
…
interrupt_clic.c
feat(esp_tee): Support for ESP32-C5 - the rest of the components
2025-08-13 14:08:59 +05:30
interrupt_intc.c
…
interrupt_plic.c
…
interrupt.c
…
linker.lf
refactor(esp32c61): bus_monitor backward compatible refactor
2025-04-08 22:50:04 +08:00
rv_utils.c
refactor(esp32c61): bus_monitor backward compatible refactor
2025-04-08 22:50:04 +08:00
vectors_clic.S
change(riscv): Remove redundant definition of MEMPROT_ISR
2025-08-04 11:43:01 +05:30
vectors_intc.S
refactor(esp_system): Update all references of the memory protection configs
2025-08-04 11:43:01 +05:30
vectors.S
fix(esp_hw_support): resolved setting mie to disable interrupts failed in sleep flow
2025-11-04 21:09:32 +08:00
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