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ec68cb3300
This option replaces implementations of functions from ROM: - memcpy - memcmp - memmove - str[n]cpy - str[n]cmp The functions used in the firmware will be better optimized for misaligned memory. Here are some measurements in CPU cycles for 4096-byte buffers: memcpy: 28676 -> 4128 memcmp: 49147 -> 14259 memmove: 33896 -> 8086 strcpy: 32771 -> 17313 strcmp: 32775 -> 13191
30 lines
2.2 KiB
C
30 lines
2.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
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#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
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#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
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#define ESP_ROM_USB_SERIAL_DEVICE_NUM (6) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
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#define ESP_ROM_USB_OTG_NUM (5) // The serial port ID (UART, USB, ...) of USB_OTG_CDC in the ROM.
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#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
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#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
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#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
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#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
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#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
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#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
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#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock
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#define ESP_ROM_HAS_LP_ROM (1) // ROM also has a LP ROM placed in LP memory
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#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs
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#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included
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#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions
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#define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version
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#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information
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#define ESP_ROM_CLIC_INT_TYPE_PATCH (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid
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#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
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#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
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