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40 lines
1.5 KiB
ReStructuredText
40 lines
1.5 KiB
ReStructuredText
SPI Features
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============
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.. _spi_master_features:
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SPI Master
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----------
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.. _spi_bus_lock:
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SPI Bus Lock
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^^^^^^^^^^^^
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To realize the multiplexing of different devices from different drivers (SPI Master, SPI Flash,
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etc.), an SPI bus lock is applied on each SPI bus. Drivers can attach their devices onto the bus
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with the arbitration of the lock.
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Each bus lock are initialized with a BG (background) service registered, all devices request to
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do transactions on the bus should wait until the BG to be successfully disabled.
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- For SPI1 bus, the BG is the cache, the bus lock will help to disable the cache before device
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operations starts, and enable it again after device releasing the lock. No devices on SPI1 is
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allowed using ISR (it's meaningless for the task to yield to other tasks when the cache is
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disabled).
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.. only:: esp32
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There are quite a few limitations when using SPI Master driver on the SPI1 bus, see
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:ref:`spi_master_on_spi1_bus`.
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.. only:: esp32s2
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The SPI Master driver hasn't supported SPI1 bus. Only SPI Flash driver can attach to the bus.
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- For other buses, the driver may register its ISR as the BG. The bus lock will block a device
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task when it requests for exclusive use of the bus, try to disable the ISR, and unblock the
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device task allowed to exclusively use the bus when the ISR is successfully disabled. When the
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task releases the lock, the lock will also try to resume the ISR if there are pending
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transactions to be done in the ISR.
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