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229 lines
8.3 KiB
C
229 lines
8.3 KiB
C
/*
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Tests for the spi sio mode
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*/
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#include <esp_types.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <malloc.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "unity.h"
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#include "driver/spi_master.h"
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#include "driver/spi_slave.h"
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#include "esp_heap_caps.h"
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#include "esp_log.h"
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#include "soc/spi_periph.h"
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#include "test_utils.h"
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#include "test/test_common_spi.h"
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#include "soc/gpio_periph.h"
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#include "hal/spi_ll.h"
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
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#if !DISABLED_FOR_TARGETS(ESP32C3) //There is only one GPSPI controller, so single-board test is disabled.
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/********************************************************************************
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* Test SIO
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********************************************************************************/
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TEST_CASE("local test sio", "[spi]")
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{
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spi_device_handle_t spi;
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WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
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WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
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uint32_t pre_set[16] = {[0 ... 15] = 0xcccccccc,};
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spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SPI_HOST), (uint8_t*)pre_set, 16*32);
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spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SLAVE_HOST), (uint8_t*)pre_set, 16*32);
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/* This test use a strange connection to test the SIO mode:
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* master spid -> slave spid
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* slave spiq -> master spid
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*/
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
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slv_cfg.spics_io_num = dev_cfg.spics_io_num;
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TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0));
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int miso_io_num = bus_cfg.miso_io_num;
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int mosi_io_num = bus_cfg.mosi_io_num;
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bus_cfg.mosi_io_num = miso_io_num;
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bus_cfg.miso_io_num = -1;
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0));
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
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spitest_gpio_output_sel(mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
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spitest_gpio_output_sel(miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
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spitest_gpio_output_sel(dev_cfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]);
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spitest_gpio_output_sel(bus_cfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out);
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for (int i = 0; i < 8; i ++) {
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int tlen = i*2+1;
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int rlen = 9-i;
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ESP_LOGI(MASTER_TAG, "=========== TEST%d ==========", i);
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spi_transaction_t master_t = {
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.length = tlen*8,
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.tx_buffer = spitest_master_send+i,
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.rxlength = rlen*8,
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.rx_buffer = master_rx_buffer+i,
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};
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spi_slave_transaction_t slave_t = {
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.length = (tlen+rlen)*8,
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.tx_buffer = spitest_slave_send+i,
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.rx_buffer = slave_rx_buffer,
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};
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memset(master_rx_buffer, 0x66, sizeof(master_rx_buffer));
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memset(slave_rx_buffer, 0x66, sizeof(slave_rx_buffer));
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY));
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TEST_ESP_OK(spi_device_transmit(spi, &master_t));
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spi_slave_transaction_t* ret_t;
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TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY));
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TEST_ASSERT(ret_t == &slave_t);
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ESP_LOG_BUFFER_HEXDUMP("master tx", master_t.tx_buffer, tlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("slave rx", slave_t.rx_buffer, tlen+rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("slave tx", slave_t.tx_buffer, tlen+rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("master rx", master_t.rx_buffer, rlen, ESP_LOG_INFO);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(master_t.tx_buffer, slave_t.rx_buffer, tlen);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t.tx_buffer + tlen, master_t.rx_buffer, rlen);
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}
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spi_slave_free(TEST_SLAVE_HOST);
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master_free_device_bus(spi);
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}
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#endif //!DISABLED_FOR_TARGETS(ESP32C3) //There is only one GPSPI controller, so single-board test is disabled.
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
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//These tests are ESP32 only due to lack of runners
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/********************************************************************************
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* Test SIO Master & Slave
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********************************************************************************/
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//if test_mosi is false, test on miso of slave, otherwise test on mosi of slave
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void test_sio_master_round(bool test_mosi)
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{
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spi_device_handle_t spi;
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WORD_ALIGNED_ATTR uint8_t rx_buffer[320];
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if (test_mosi) {
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ESP_LOGI(MASTER_TAG, "======== TEST MOSI ===========");
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} else {
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ESP_LOGI(MASTER_TAG, "======== TEST MISO ===========");
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}
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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if (!test_mosi) bus_cfg.mosi_io_num = bus_cfg.miso_io_num;
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bus_cfg.miso_io_num = -1;
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0));
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
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dev_cfg.clock_speed_hz = 1*1000*1000;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
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for (int i = 0; i < 8; i ++) {
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int tlen = i*2+1;
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int rlen = 9-i;
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spi_transaction_t t = {
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.length = tlen*8,
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.tx_buffer = spitest_master_send+i,
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.rxlength = rlen*8,
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.rx_buffer = rx_buffer+i,
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};
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memset(rx_buffer, 0x66, sizeof(rx_buffer));
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//get signal
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unity_wait_for_signal("slave ready");
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TEST_ESP_OK(spi_device_transmit(spi, &t));
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uint8_t* exp_ptr = spitest_slave_send+i;
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ESP_LOG_BUFFER_HEXDUMP("master tx", t.tx_buffer, tlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("master rx", t.rx_buffer, rlen, ESP_LOG_INFO);
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if (!test_mosi) {
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TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr+tlen, t.rx_buffer, rlen);
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}
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}
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master_free_device_bus(spi);
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}
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void test_sio_master(void)
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{
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test_sio_master_round(true);
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unity_send_signal("master ready");
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test_sio_master_round(false);
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}
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void test_sio_slave_round(bool test_mosi)
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{
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WORD_ALIGNED_ATTR uint8_t rx_buffer[320];
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if (test_mosi) {
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ESP_LOGI(SLAVE_TAG, "======== TEST MOSI ===========");
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} else {
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ESP_LOGI(SLAVE_TAG, "======== TEST MISO ===========");
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}
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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bus_cfg.mosi_io_num = spi_periph_signal[TEST_SLAVE_HOST].spid_iomux_pin;
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bus_cfg.miso_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiq_iomux_pin;
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bus_cfg.sclk_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiclk_iomux_pin;
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spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
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slv_cfg.spics_io_num = spi_periph_signal[TEST_SLAVE_HOST].spics0_iomux_pin;
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TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0));
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for (int i = 0; i < 8; i++) {
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int tlen = 9-i;
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int rlen = i*2+1;
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spi_slave_transaction_t t = {
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.length = (tlen+rlen)*8,
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.tx_buffer = spitest_slave_send+i,
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.rx_buffer = rx_buffer,
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};
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &t, portMAX_DELAY));
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ESP_LOG_BUFFER_HEXDUMP("slave tx", t.tx_buffer, tlen+rlen, ESP_LOG_INFO);
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//send signal_idx
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unity_send_signal("slave ready");
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uint8_t *exp_ptr = spitest_master_send+i;
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spi_slave_transaction_t* ret_t;
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TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY));
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ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, tlen+rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("slave rx", t.rx_buffer, tlen+rlen, ESP_LOG_INFO);
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if (test_mosi) {
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TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr, t.rx_buffer, rlen);
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}
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}
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spi_slave_free(TEST_SLAVE_HOST);
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}
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void test_sio_slave(void)
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{
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test_sio_slave_round(true);
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unity_wait_for_signal("master ready");
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test_sio_slave_round(false);
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}
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TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave);
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#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
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#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
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