mirror of
https://github.com/espressif/esp-idf.git
synced 2025-09-10 00:42:48 +00:00
335027b731
Previously, as DMA descriptors were processed, the task performing SDMMC transfer would get woken up and would refill the descriptors. This design didn't work correctly when higher priority tasks occupied the CPU for too long, resulting in SDMMC transfer timing out. This change moves DMA descriptor refilling into SDMMC ISR. Now the "DMA done" interrupt is delivered back to task context only when the entire transfer is completed. Closes https://github.com/espressif/esp-idf/issues/13934
772 lines
19 KiB
C
772 lines
19 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "esp_bit_defs.h"
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "hal/sd_types.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/sdmmc_struct.h"
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#include "soc/sdmmc_reg.h"
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#include "soc/system_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SDMMC_LL_GET_HW(id) (((id) == 0) ? (&SDMMC) : NULL)
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#define SDMMC_LL_EVENT_IO_SLOT1 (1<<17)
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#define SDMMC_LL_EVENT_IO_SLOT0 (1<<16)
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#define SDMMC_LL_EVENT_EBE (1<<15)
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#define SDMMC_LL_EVENT_ACD (1<<14)
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#define SDMMC_LL_EVENT_SBE (1<<13)
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#define SDMMC_LL_EVENT_BCI (1<<13)
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#define SDMMC_LL_EVENT_HLE (1<<12)
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#define SDMMC_LL_EVENT_FRUN (1<<11)
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#define SDMMC_LL_EVENT_HTO (1<<10)
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#define SDMMC_LL_EVENT_DTO (1<<9)
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#define SDMMC_LL_EVENT_RTO (1<<8)
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#define SDMMC_LL_EVENT_DCRC (1<<7)
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#define SDMMC_LL_EVENT_RCRC (1<<6)
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#define SDMMC_LL_EVENT_RXDR (1<<5)
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#define SDMMC_LL_EVENT_TXDR (1<<4)
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#define SDMMC_LL_EVENT_DATA_OVER (1<<3)
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#define SDMMC_LL_EVENT_CMD_DONE (1<<2)
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#define SDMMC_LL_EVENT_RESP_ERR (1<<1)
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#define SDMMC_LL_EVENT_CD (1<<0)
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/* Default disabled interrupts (on init):
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* SDMMC_LL_EVENT_RXDR,
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* SDMMC_LL_EVENT_TXDR,
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* SDMMC_LL_EVENT_BCI,
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* SDMMC_LL_EVENT_ACD,
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* SDMMC_LL_EVENT_IO_SLOT1,
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* SDMMC_LL_EVENT_IO_SLOT0
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*/
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// Default enabled interrupts (sdio is enabled only when use):
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#define SDMMC_LL_EVENT_DEFAULT \
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(SDMMC_LL_EVENT_CD | SDMMC_LL_EVENT_RESP_ERR | SDMMC_LL_EVENT_CMD_DONE | SDMMC_LL_EVENT_DATA_OVER | \
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SDMMC_LL_EVENT_RCRC | SDMMC_LL_EVENT_DCRC | SDMMC_LL_EVENT_RTO | SDMMC_LL_EVENT_DTO | SDMMC_LL_EVENT_HTO | \
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SDMMC_LL_EVENT_HLE | \
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SDMMC_LL_EVENT_SBE | \
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SDMMC_LL_EVENT_EBE)
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#define SDMMC_LL_SD_EVENT_MASK \
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(SDMMC_LL_EVENT_CD | SDMMC_LL_EVENT_RESP_ERR | SDMMC_LL_EVENT_CMD_DONE | SDMMC_LL_EVENT_DATA_OVER | \
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SDMMC_LL_EVENT_TXDR | SDMMC_LL_EVENT_RXDR |\
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SDMMC_LL_EVENT_RCRC | SDMMC_LL_EVENT_DCRC | SDMMC_LL_EVENT_RTO | SDMMC_LL_EVENT_DTO | SDMMC_LL_EVENT_HTO | \
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SDMMC_LL_EVENT_FRUN | SDMMC_LL_EVENT_HLE |\
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SDMMC_LL_EVENT_SBE | SDMMC_LL_EVENT_ACD |\
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SDMMC_LL_EVENT_EBE)
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// DMA interrupts (idsts register)
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#define SDMMC_LL_EVENT_DMA_TI SDMMC_IDMAC_INTMASK_TI
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#define SDMMC_LL_EVENT_DMA_RI SDMMC_IDMAC_INTMASK_RI
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#define SDMMC_LL_EVENT_DMA_NI SDMMC_IDMAC_INTMASK_NI
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#define SDMMC_LL_EVENT_DMA_MASK 0x1f //NI and AI will be indicated by TI/RI and FBE/DU respectively
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/**
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* SDMMC capabilities
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*/
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#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) 1
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#define SDMMC_LL_IOMUX_FUNC -1
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typedef enum {
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SDMMC_LL_DELAY_PHASE_0,
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SDMMC_LL_DELAY_PHASE_1,
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SDMMC_LL_DELAY_PHASE_2,
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SDMMC_LL_DELAY_PHASE_3,
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} sdmmc_ll_delay_phase_t;
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/*---------------------------------------------------------------
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Clock & Reset
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---------------------------------------------------------------*/
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/**
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* @brief Enable the bus clock for SDMMC module
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*
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* @param hw hardware instance address
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
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{
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SYSTEM.perip_clk_en1.sdio_host_clk_en = en;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the SDMMC module
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
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{
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SYSTEM.perip_rst_en1.sdio_host_rst = 1;
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SYSTEM.perip_rst_en1.sdio_host_rst = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdmmc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_reset_register(__VA_ARGS__)
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/**
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* @brief Select SDMMC clock source
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*
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* @param hw hardware instance address
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* @param clk_src clock source, see valid sources in type `soc_periph_psram_clk_src_t`
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*/
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static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_clk_src_t clk_src)
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{
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uint32_t clk_val = 0;
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switch (clk_src) {
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case SDMMC_CLK_SRC_PLL160M:
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clk_val = 1;
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break;
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case SDMMC_CLK_SRC_XTAL:
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clk_val = 0;
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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hw->clock.clk_sel = clk_val;
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}
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/**
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* @brief Set SDMMC clock div
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*
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* @param hw hardware instance address
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* @param div divider value
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*/
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static inline void sdmmc_ll_set_clock_div(sdmmc_dev_t *hw, uint32_t div)
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{
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/**
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* Set frequency to 160MHz / div
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*
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* n: counter resets at div_factor_n.
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* l: negedge when counter equals div_factor_l.
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* h: posedge when counter equals div_factor_h.
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*
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* We set the duty cycle to 1/2
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*/
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HAL_ASSERT(div > 1 && div <= 16);
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int l = div - 1;
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int h = div / 2 - 1;
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hw->clock.div_factor_h = h;
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hw->clock.div_factor_l = l;
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hw->clock.div_factor_n = l;
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}
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/**
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* @brief Deinit clock
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_deinit_clk(sdmmc_dev_t *hw)
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{
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hw->clock.val = 0;
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}
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/**
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* @brief Get SDMMC clock div
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*
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* @param hw hardware instance address
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*
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* @return Divider value
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*/
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static inline uint32_t sdmmc_ll_get_clock_div(sdmmc_dev_t *hw)
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{
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return hw->clock.div_factor_l + 1;
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}
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/**
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* @brief Initialise the din, dout, self delay phase
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
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{
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hw->clock.phase_core = 0;
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/* 90 deg. delay for cclk_out to satisfy large hold time for SDR12 (up to 25MHz) and SDR25 (up to 50MHz) modes.
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* Whether this delayed clock will be used depends on use_hold_reg bit in CMD structure,
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* determined when sending out the command.
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*/
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hw->clock.phase_dout = 1;
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hw->clock.phase_din = 0;
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}
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/**
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* @brief Set SDMMC din delay
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*
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* @param hw hardware instance address
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* @param phase delay phase
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*/
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static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase)
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{
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switch (phase) {
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case SDMMC_LL_DELAY_PHASE_1:
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hw->clock.phase_din = 0x1;
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break;
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case SDMMC_LL_DELAY_PHASE_2:
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hw->clock.phase_din = 0x4;
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break;
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case SDMMC_LL_DELAY_PHASE_3:
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hw->clock.phase_din = 0x6;
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break;
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default:
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hw->clock.phase_din = 0x0;
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break;
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}
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}
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/**
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* @brief Enable card clock
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_card_clock(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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uint32_t reg_val = HAL_FORCE_READ_U32_REG_FIELD(hw->clkena, cclk_enable);
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if (en) {
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reg_val |= BIT(slot);
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} else {
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reg_val &= ~BIT(slot);
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkena, cclk_enable, reg_val);
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}
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/**
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* @brief Set card clock div
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param card_div divider value
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*/
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static inline void sdmmc_ll_set_card_clock_div(sdmmc_dev_t *hw, uint32_t slot, uint32_t card_div)
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{
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if (slot == 0) {
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hw->clksrc.card0 = 0;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkdiv, div0, card_div);
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} else if (slot == 1) {
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hw->clksrc.card1 = 1;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkdiv, div1, card_div);
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} else {
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HAL_ASSERT(false);
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}
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}
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/**
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* @brief Get card clock div
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*
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* @param hw hardware instance address
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* @param slot slot
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*
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* @return Divider value
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*/
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static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slot)
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{
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uint32_t card_div = 0;
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if (slot == 0) {
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HAL_ASSERT(hw->clksrc.card0 == 0);
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card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div0);
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} else if (slot == 1) {
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HAL_ASSERT(hw->clksrc.card1 == 1);
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card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div1);
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} else {
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HAL_ASSERT(false);
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}
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return card_div;
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}
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/**
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* @brief Disable clock when the card is in IDLE state
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_card_clock_low_power(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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uint32_t reg_val = HAL_FORCE_READ_U32_REG_FIELD(hw->clkena, cclk_low_power);
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if (en) {
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reg_val |= BIT(slot);
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} else {
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reg_val &= ~BIT(slot);
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkena, cclk_low_power, reg_val);
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}
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/**
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* @brief Reset controller
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*
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* @note Self clear after two AHB clock cycles, needs wait done
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_reset_controller(sdmmc_dev_t *hw)
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{
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hw->ctrl.controller_reset = 1;
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}
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/**
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* @brief Get if controller reset is done
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*
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* @param hw hardware instance address
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*
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* @return true: done; false: not done
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*/
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static inline bool sdmmc_ll_is_controller_reset_done(sdmmc_dev_t *hw)
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{
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return hw->ctrl.controller_reset == 0;
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}
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/**
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* @brief Reset DMA
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*
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* @note Self clear after two AHB clock cycles, needs wait done
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_reset_dma(sdmmc_dev_t *hw)
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{
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hw->ctrl.dma_reset = 1;
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}
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/**
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* @brief Get if dma reset is done
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*
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* @param hw hardware instance address
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*
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* @return true: done; false: not done
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*/
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static inline bool sdmmc_ll_is_dma_reset_done(sdmmc_dev_t *hw)
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{
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return hw->ctrl.dma_reset == 0;
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}
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/**
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* @brief Reset fifo
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*
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* @note Self clear after reset done, needs wait done
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*
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* @param hw hardware instance address
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*/
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static inline void sdmmc_ll_reset_fifo(sdmmc_dev_t *hw)
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{
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hw->ctrl.fifo_reset = 1;
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}
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/**
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* @brief Get if fifo reset is done
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*
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* @param hw hardware instance address
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*
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* @return true: done; false: not done
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*/
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static inline bool sdmmc_ll_is_fifo_reset_done(sdmmc_dev_t *hw)
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{
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return hw->ctrl.fifo_reset == 0;
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}
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/*---------------------------------------------------------------
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MISC
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---------------------------------------------------------------*/
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/**
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* @brief Set card data read timeout cycles
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*
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* @param hw hardware instance address
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* @param timeout_cycles timeout cycles
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*/
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static inline void sdmmc_ll_set_data_timeout(sdmmc_dev_t *hw, uint32_t timeout_cycles)
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{
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if (timeout_cycles > 0xffffff) {
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timeout_cycles = 0xffffff;
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}
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hw->tmout.data = timeout_cycles;
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}
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/**
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* @brief Set response timeout cycles (in card output clocks)
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*
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* @param hw hardware instance address
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* @param timeout_cycles timeout cycles
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*/
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static inline void sdmmc_ll_set_response_timeout(sdmmc_dev_t *hw, uint32_t timeout_cycles)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tmout, response, timeout_cycles);
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}
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/**
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* @brief Check if card is detected
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*
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* @param hw hardware instance address
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* @param slot slot
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*
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* @return True for detected
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*/
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static inline bool sdmmc_ll_is_card_detected(sdmmc_dev_t *hw, uint32_t slot)
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{
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return ((hw->cdetect.cards & BIT(slot)) == 0);
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}
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/**
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* @brief Check if card is write protected
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*
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* @param hw hardware instance address
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* @param slot slot
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*
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* @return True for write protected
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*/
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static inline bool sdmmc_ll_is_card_write_protected(sdmmc_dev_t *hw, uint32_t slot)
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{
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bool is_protected = hw->wrtprt.cards & BIT(slot);
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return is_protected;
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}
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/**
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* @brief Switch between 3.3V and 1.8V mode
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable 1.8V (3.3V on disable)
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*/
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static inline void sdmmc_ll_enable_1v8_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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//for compatibility
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}
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/**
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* @brief Enable DDR mode
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*
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* @param hw hardware instance address
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* @param slot slot
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* @param en enable / disable
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*/
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static inline void sdmmc_ll_enable_ddr_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
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{
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uint32_t ddr_reg_val = HAL_FORCE_READ_U32_REG_FIELD(hw->uhs, ddr);
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if (en) {
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ddr_reg_val|= BIT(slot);
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->uhs, ddr, ddr_reg_val);
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hw->emmc_ddr_reg |= BIT(slot);
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} else {
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ddr_reg_val&= ~BIT(slot);
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->uhs, ddr, ddr_reg_val);
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hw->emmc_ddr_reg &= ~BIT(slot);
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}
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}
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/**
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* @brief Set data transfer length
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*
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* @param hw hardware instance address
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* @param len length
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*/
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static inline void sdmmc_ll_set_data_transfer_len(sdmmc_dev_t *hw, uint32_t len)
|
|
{
|
|
hw->bytcnt = len;
|
|
}
|
|
|
|
/**
|
|
* @brief Set block size
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param block_size block size
|
|
*/
|
|
static inline void sdmmc_ll_set_block_size(sdmmc_dev_t *hw, uint32_t block_size)
|
|
{
|
|
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blksiz, block_size, block_size);
|
|
}
|
|
|
|
/**
|
|
* @brief Set descriptor addr
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param block_size block size
|
|
*/
|
|
static inline void sdmmc_ll_set_desc_addr(sdmmc_dev_t *hw, uint32_t desc_addr)
|
|
{
|
|
hw->dbaddr = (sdmmc_desc_t *)desc_addr;
|
|
}
|
|
|
|
/**
|
|
* @brief Poll demand
|
|
*
|
|
* @param hw hardware instance address
|
|
*/
|
|
static inline void sdmmc_ll_poll_demand(sdmmc_dev_t *hw)
|
|
{
|
|
hw->pldmnd = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Set command
|
|
*
|
|
* @param hw hardware instance address
|
|
*/
|
|
static inline void sdmmc_ll_set_command(sdmmc_dev_t *hw, sdmmc_hw_cmd_t cmd)
|
|
{
|
|
memcpy((void *)&hw->cmd, &cmd, sizeof(sdmmc_hw_cmd_t));
|
|
}
|
|
|
|
/**
|
|
* @brief Get if command is taken by CIU
|
|
*
|
|
* @param hw hardware instance address
|
|
*
|
|
* @return 1: is taken; 0: not taken, should not write to any command regs
|
|
*/
|
|
static inline bool sdmmc_ll_is_command_taken(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->cmd.start_command == 0;
|
|
}
|
|
|
|
/**
|
|
* @brief Set command argument
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param arg value indicates command argument to be passed to card
|
|
*/
|
|
static inline void sdmmc_ll_set_command_arg(sdmmc_dev_t *hw, uint32_t arg)
|
|
{
|
|
hw->cmdarg = arg;
|
|
}
|
|
|
|
/**
|
|
* @brief Get version ID
|
|
*
|
|
* @param hw hardware instance address
|
|
*
|
|
* @return version ID
|
|
*/
|
|
static inline uint32_t sdmmc_ll_get_version_id(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->verid;
|
|
}
|
|
|
|
/**
|
|
* @brief Get hardware configuration info
|
|
*
|
|
* @param hw hardware instance address
|
|
*
|
|
* @return hardware configurations
|
|
*/
|
|
static inline uint32_t sdmmc_ll_get_hw_config_info(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->hcon.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Set card width
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param slot slot ID
|
|
* @param width card width
|
|
*/
|
|
static inline void sdmmc_ll_set_card_width(sdmmc_dev_t *hw, uint32_t slot, sd_bus_width_t width)
|
|
{
|
|
uint16_t mask = 1 << slot;
|
|
uint32_t reg_val = HAL_FORCE_READ_U32_REG_FIELD(hw->ctype, card_width);
|
|
uint32_t reg_val_8 = HAL_FORCE_READ_U32_REG_FIELD(hw->ctype, card_width_8);
|
|
|
|
switch (width) {
|
|
case SD_BUS_WIDTH_1_BIT:
|
|
reg_val_8 &= ~mask;
|
|
reg_val &= ~mask;
|
|
break;
|
|
case SD_BUS_WIDTH_4_BIT:
|
|
reg_val_8 &= ~mask;
|
|
reg_val |= mask;
|
|
break;
|
|
case SD_BUS_WIDTH_8_BIT:
|
|
reg_val_8 |= mask;
|
|
break;
|
|
default:
|
|
HAL_ASSERT(false);
|
|
}
|
|
|
|
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->ctype, card_width, reg_val);
|
|
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->ctype, card_width_8, reg_val_8);
|
|
}
|
|
|
|
/**
|
|
* @brief Is card data busy
|
|
*
|
|
* @param hw hardware instance address
|
|
*
|
|
* @return 1: busy; 0: idle
|
|
*/
|
|
static inline bool sdmmc_ll_is_card_data_busy(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->status.data_busy == 1;
|
|
}
|
|
|
|
/*---------------------------------------------------------------
|
|
DMA
|
|
---------------------------------------------------------------*/
|
|
/**
|
|
* @brief Init DMA
|
|
* - enable dma
|
|
* - clear bus mode reg and reset all dmac internal regs
|
|
* - enable internal dmac interrupt
|
|
*
|
|
* @param hw hardware instance address
|
|
*/
|
|
static inline void sdmmc_ll_init_dma(sdmmc_dev_t *hw)
|
|
{
|
|
hw->ctrl.dma_enable = 1;
|
|
hw->bmod.val = 0;
|
|
hw->bmod.sw_reset = 1;
|
|
hw->idinten.ni = 1;
|
|
hw->idinten.ri = 1;
|
|
hw->idinten.ti = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable DMA
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param en enable / disable
|
|
*/
|
|
static inline void sdmmc_ll_enable_dma(sdmmc_dev_t *hw, bool en)
|
|
{
|
|
hw->ctrl.dma_enable = en;
|
|
hw->ctrl.use_internal_dma = en;
|
|
hw->bmod.enable = en;
|
|
hw->bmod.fb = en;
|
|
}
|
|
|
|
/**
|
|
* @brief Stop DMA
|
|
*
|
|
* @param hw hardware instance address
|
|
*/
|
|
static inline void sdmmc_ll_stop_dma(sdmmc_dev_t *hw)
|
|
{
|
|
hw->ctrl.use_internal_dma = 0;
|
|
hw->ctrl.dma_reset = 1; //here might be an issue as we don't wait the `dma_reset` to be self-cleared, check in next steps
|
|
hw->bmod.fb = 0;
|
|
hw->bmod.enable = 0;
|
|
}
|
|
|
|
/*---------------------------------------------------------------
|
|
INTR
|
|
---------------------------------------------------------------*/
|
|
/**
|
|
* @brief Get masked interrupt-status register value
|
|
*
|
|
* @param hw hardware instance address
|
|
*/
|
|
static inline uint32_t sdmmc_ll_get_intr_status(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->mintsts.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable interrupt
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param mask interrupt mask
|
|
* @param en enable / disable
|
|
*/
|
|
static inline void sdmmc_ll_enable_interrupt(sdmmc_dev_t *hw, uint32_t mask, bool en)
|
|
{
|
|
if (en) {
|
|
hw->intmask.val |= mask;
|
|
} else {
|
|
hw->intmask.val &= ~mask;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Get RAW interrupt-status register value
|
|
*/
|
|
static inline uint32_t sdmmc_ll_get_interrupt_raw(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->rintsts.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear interrupt
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param mask interrupt mask
|
|
*/
|
|
static inline void sdmmc_ll_clear_interrupt(sdmmc_dev_t *hw, uint32_t mask)
|
|
{
|
|
hw->rintsts.val = mask;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable / disable interrupts globally
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param en enable / disable
|
|
*/
|
|
static inline void sdmmc_ll_enable_global_interrupt(sdmmc_dev_t *hw, bool en)
|
|
{
|
|
hw->ctrl.int_enable = (uint32_t)en;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Enable / disable busy clear interrupt
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param en enable / disable
|
|
*/
|
|
static inline void sdmmc_ll_enable_busy_clear_interrupt(sdmmc_dev_t *hw, bool en)
|
|
{
|
|
hw->cardthrctl.busy_clr_int_en = en;
|
|
}
|
|
|
|
/**
|
|
* @brief Get internal dmac status register val
|
|
*/
|
|
static inline uint32_t sdmmc_ll_get_idsts_interrupt_raw(sdmmc_dev_t *hw)
|
|
{
|
|
return hw->idsts.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear internal dmac status register events
|
|
*
|
|
* @param hw hardware instance address
|
|
* @param mask interrupt mask
|
|
*/
|
|
static inline void sdmmc_ll_clear_idsts_interrupt(sdmmc_dev_t *hw, uint32_t mask)
|
|
{
|
|
hw->idsts.val = mask;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|