mirror of
https://github.com/espressif/esp-idf.git
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272 lines
8.7 KiB
C
272 lines
8.7 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Register */
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/** Type of sys_external_device_encrypt_decrypt_control register
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* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
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*/
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typedef union {
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struct {
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/** sys_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
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* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
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*/
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uint32_t sys_enable_spi_manual_encrypt:1;
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/** sys_enable_download_db_encrypt : HRO; bitpos: [1]; default: 0;
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* reserved
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*/
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uint32_t sys_enable_download_db_encrypt:1;
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/** sys_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
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* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
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*/
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uint32_t sys_enable_download_g0cb_decrypt:1;
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/** sys_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
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* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
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*/
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uint32_t sys_enable_download_manual_encrypt:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} hp_sys_external_device_encrypt_decrypt_control_reg_t;
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/** Type of sys_sram_usage_conf register
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* HP memory usage configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:10;
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/** sys_sram_usage : R/W; bitpos: [14:10]; default: 0;
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* 0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
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*/
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uint32_t sys_sram_usage:5;
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uint32_t reserved_15:5;
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/** sys_mac_dump_alloc : R/W; bitpos: [24:20]; default: 0;
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* reserved.
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*/
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uint32_t sys_mac_dump_alloc:5;
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uint32_t reserved_25:7;
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};
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uint32_t val;
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} hp_sys_sram_usage_conf_reg_t;
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/** Type of sys_sec_dpa_conf register
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* HP anti-DPA security configuration register
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*/
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typedef union {
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struct {
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/** sys_sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
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* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
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* the number, the stronger the ability to resist DPA attacks and the higher the
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* security level, but it will increase the computational overhead of the hardware
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* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
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*/
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uint32_t sys_sec_dpa_level:2;
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/** sys_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
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* This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
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* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
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*/
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uint32_t sys_sec_dpa_cfg_sel:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} hp_sys_sec_dpa_conf_reg_t;
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/** Type of sys_rom_table_lock register
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* Rom-Table lock register
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*/
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typedef union {
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struct {
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/** sys_rom_table_lock : R/W; bitpos: [0]; default: 0;
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* XXXX
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*/
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uint32_t sys_rom_table_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_sys_rom_table_lock_reg_t;
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/** Type of sys_rom_table register
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* Rom-Table register
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*/
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typedef union {
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struct {
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/** sys_rom_table : R/W; bitpos: [31:0]; default: 0;
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* XXXX
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*/
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uint32_t sys_rom_table:32;
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};
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uint32_t val;
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} hp_sys_rom_table_reg_t;
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/** Type of sys_rng_loop register
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* configure rng_ring
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*/
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typedef union {
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struct {
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uint32_t reserved_0:24;
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/** sys_sample_cnt : RO; bitpos: [31:24]; default: 0;
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* This field get rng ring count
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*/
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uint32_t sys_sample_cnt:8;
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};
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uint32_t val;
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} hp_sys_rng_loop_reg_t;
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/** Group: Timeout Register */
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/** Type of sys_cpu_peri_timeout_conf register
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* CPU_PERI_TIMEOUT configuration register
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*/
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typedef union {
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struct {
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/** sys_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
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* Set the timeout threshold for bus access, corresponding to the number of clock
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* cycles of the clock domain.
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*/
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uint32_t sys_cpu_peri_timeout_thres:16;
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/** sys_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
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* Set this bit as 1 to clear timeout interrupt
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*/
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uint32_t sys_cpu_peri_timeout_int_clear:1;
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/** sys_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
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* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
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* registers
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*/
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uint32_t sys_cpu_peri_timeout_protect_en:1;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} hp_sys_cpu_peri_timeout_conf_reg_t;
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/** Type of sys_cpu_peri_timeout_addr register
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* CPU_PERI_TIMEOUT_ADDR register
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*/
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typedef union {
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struct {
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/** sys_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
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* Record the address information of abnormal access
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*/
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uint32_t sys_cpu_peri_timeout_addr:32;
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};
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uint32_t val;
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} hp_sys_cpu_peri_timeout_addr_reg_t;
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/** Type of sys_cpu_peri_timeout_uid register
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* CPU_PERI_TIMEOUT_UID register
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*/
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typedef union {
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struct {
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/** sys_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
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* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
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* will be cleared after the interrupt is cleared.
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*/
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uint32_t sys_cpu_peri_timeout_uid:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} hp_sys_cpu_peri_timeout_uid_reg_t;
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/** Type of sys_hp_peri_timeout_conf register
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* HP_PERI_TIMEOUT configuration register
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*/
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typedef union {
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struct {
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/** sys_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
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* Set the timeout threshold for bus access, corresponding to the number of clock
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* cycles of the clock domain.
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*/
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uint32_t sys_hp_peri_timeout_thres:16;
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/** sys_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
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* Set this bit as 1 to clear timeout interrupt
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*/
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uint32_t sys_hp_peri_timeout_int_clear:1;
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/** sys_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
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* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
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*/
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uint32_t sys_hp_peri_timeout_protect_en:1;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} hp_sys_hp_peri_timeout_conf_reg_t;
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/** Type of sys_hp_peri_timeout_addr register
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* HP_PERI_TIMEOUT_ADDR register
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*/
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typedef union {
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struct {
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/** sys_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
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* Record the address information of abnormal access
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*/
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uint32_t sys_hp_peri_timeout_addr:32;
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};
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uint32_t val;
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} hp_sys_hp_peri_timeout_addr_reg_t;
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/** Type of sys_hp_peri_timeout_uid register
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* HP_PERI_TIMEOUT_UID register
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*/
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typedef union {
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struct {
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/** sys_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
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* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
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* will be cleared after the interrupt is cleared.
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*/
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uint32_t sys_hp_peri_timeout_uid:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} hp_sys_hp_peri_timeout_uid_reg_t;
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/** Group: Version Register */
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/** Type of sys_date register
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* Date register.
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*/
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typedef union {
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struct {
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/** sys_date : R/W; bitpos: [27:0]; default: 37782128;
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* HP-SYSTEM date information/ HP-SYSTEM version information.
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*/
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uint32_t sys_date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} hp_sys_date_reg_t;
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typedef struct {
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volatile hp_sys_external_device_encrypt_decrypt_control_reg_t sys_external_device_encrypt_decrypt_control;
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volatile hp_sys_sram_usage_conf_reg_t sys_sram_usage_conf;
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volatile hp_sys_sec_dpa_conf_reg_t sys_sec_dpa_conf;
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volatile hp_sys_cpu_peri_timeout_conf_reg_t sys_cpu_peri_timeout_conf;
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volatile hp_sys_cpu_peri_timeout_addr_reg_t sys_cpu_peri_timeout_addr;
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volatile hp_sys_cpu_peri_timeout_uid_reg_t sys_cpu_peri_timeout_uid;
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volatile hp_sys_hp_peri_timeout_conf_reg_t sys_hp_peri_timeout_conf;
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volatile hp_sys_hp_peri_timeout_addr_reg_t sys_hp_peri_timeout_addr;
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volatile hp_sys_hp_peri_timeout_uid_reg_t sys_hp_peri_timeout_uid;
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volatile hp_sys_rom_table_lock_reg_t sys_rom_table_lock;
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volatile hp_sys_rom_table_reg_t sys_rom_table;
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uint32_t reserved_02c;
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volatile hp_sys_rng_loop_reg_t sys_rng_loop;
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uint32_t reserved_034[242];
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volatile hp_sys_date_reg_t sys_date;
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} hp_system_dev_t;
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extern hp_system_dev_t HP_SYSTEM;
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#ifndef __cplusplus
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_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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