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Initially, ESP-IDF used the do_global_ctors() function to run global constructors. This was done to accommodate Xtensa targets that emit .ctors.* sections, which are ordered in descending order. For RISC-V, compilation used .init_array.* sections, which are designed to have ascending order. Priority constructors in .init_array.* sections were correctly processed in ascending order. However, non-priority .init_array section was processed in descending order, as it was done for Xtensa .ctors. Starting with ESP-IDF v6.0, the implementation switched to the standard LibC behavior (__libc_init_array()), which processes both priority and non-priority constructors in ascending order. To achieve this, a breaking changes were introduced: - Xtensa .ctors.* priority entries converted to .init_array.* format (ascending), to be passed to __libc_init_array(). - Processing order of non-priority .init_array and .ctors sections was changed from descending to ascending. Also, this change introduces .preinit_array for linking. This may be needed for some C++ or sanitizer features. Related to https://github.com/espressif/esp-idf/issues/15529
202 lines
6.5 KiB
C
202 lines
6.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include "esp_private/esp_system_attr.h"
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#include "esp_err.h"
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#include "esp_compiler.h"
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#include "esp_macros.h"
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#include "esp_system.h"
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#include "esp_log.h"
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "esp_cpu.h"
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#include "esp_private/startup_internal.h"
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// Ensure that system configuration matches the underlying number of cores.
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// This should enable us to avoid checking for both every time.
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#if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#error "System has been configured to run on multiple cores, but target SoC only has a single core."
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#endif
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uint64_t g_startup_time = 0;
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// App entry point for core 0
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extern void esp_startup_start_app(void);
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// Entry point for core 0 from hardware init (port layer)
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void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// Entry point for core [1..X] from hardware init (port layer)
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void start_cpu_other_cores(void) __attribute__((weak, alias("start_cpu_other_cores_default"))) __attribute__((noreturn));
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// App entry point for core [1..X]
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void esp_startup_start_app_other_cores(void) __attribute__((weak, alias("esp_startup_start_app_other_cores_default"))) __attribute__((noreturn));
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static volatile bool s_system_inited[SOC_CPU_CORES_NUM] = { false };
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const sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM] = { [0] = start_cpu0,
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#if SOC_CPU_CORES_NUM > 1
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[1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
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#endif
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};
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static volatile bool s_system_full_inited = false;
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#else
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const sys_startup_fn_t g_startup_fn[1] = { start_cpu0 };
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#endif
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static const char* TAG = "cpu_start";
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#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
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/**
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* @brief A helper function for __do_global_ctors, which is in crtend.o.
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* It has been adapted from GCC source code. In GCC, it resides under
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* the USE_EH_FRAME_REGISTRY macro, which is not enabled in Espressif
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* toolchains to save small memory amount. Nevertheless, when C++ exceptions
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* are enabled this initialization becomes necessary.
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*/
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static void __do_global_ctors_1(void)
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{
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struct object {
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long placeholder[10];
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};
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void __register_frame_info(const void *begin, struct object * ob);
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extern char __eh_frame[];
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static struct object ob;
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__register_frame_info(__eh_frame, &ob);
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}
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#endif // CONFIG_COMPILER_CXX_EXCEPTIONS
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/**
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* @brief Call component init functions defined using ESP_SYSTEM_INIT_Fn macros.
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* The esp_system_init_fn_t structures describing these functions are collected into
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* an array [_esp_system_init_fn_array_start, _esp_system_init_fn_array_end) by the
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* linker. The functions are sorted by their priority value.
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* The sequence of the init function calls (sorted by priority) is documented in
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* system_init_fn.txt file.
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* @param stage_num Stage number of the init function call (0, 1).
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*/
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__attribute__((no_sanitize_undefined)) /* TODO: IDF-8133 */
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static void do_system_init_fn(uint32_t stage_num)
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{
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extern esp_system_init_fn_t _esp_system_init_fn_array_start;
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extern esp_system_init_fn_t _esp_system_init_fn_array_end;
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esp_system_init_fn_t *p;
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int core_id = esp_cpu_get_core_id();
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for (p = &_esp_system_init_fn_array_start; p < &_esp_system_init_fn_array_end; ++p) {
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if (p->stage == stage_num && (p->cores & BIT(core_id)) != 0) {
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// During core init, stdout is not initialized yet, so use early logging.
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ESP_EARLY_LOGD(TAG, "calling init function: %p on core: %d", p->fn, core_id);
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esp_err_t err = (*(p->fn))();
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if (err != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "init function %p has failed (0x%x), aborting", p->fn, err);
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abort();
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}
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}
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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s_system_inited[core_id] = true;
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#endif
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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static void esp_startup_start_app_other_cores_default(void)
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{
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while (1) {
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esp_rom_delay_us(UINT32_MAX);
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}
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}
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/* This function has to be in IRAM, as while it is running on CPU1, CPU0 may do some flash operations
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* (e.g. initialize the core dump), which means that cache will be disabled.
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*/
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static void ESP_SYSTEM_IRAM_ATTR start_cpu_other_cores_default(void)
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{
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do_system_init_fn(ESP_SYSTEM_INIT_STAGE_SECONDARY);
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while (!s_system_full_inited) {
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esp_rom_delay_us(100);
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}
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esp_startup_start_app_other_cores();
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}
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#endif
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static void do_core_init(void)
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{
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do_system_init_fn(ESP_SYSTEM_INIT_STAGE_CORE);
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}
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static void do_secondary_init(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// The port layer transferred control to this function with other cores 'paused',
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// resume execution so that cores might execute component initialization functions.
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startup_resume_other_cores();
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#endif
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// Execute initialization functions esp_system_init_fn_t assigned to the main core. While
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// this is happening, all other cores are executing the initialization functions
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// assigned to them since they have been resumed already.
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do_system_init_fn(ESP_SYSTEM_INIT_STAGE_SECONDARY);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// Wait for all cores to finish secondary init.
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volatile bool system_inited = false;
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while (!system_inited) {
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system_inited = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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system_inited &= s_system_inited[i];
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}
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esp_rom_delay_us(100);
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}
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#endif
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}
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static void start_cpu0_default(void)
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{
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extern void __libc_init_array(void);
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// Initialize core components and services.
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// Operations that needs the cache to be disabled have to be done here.
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do_core_init();
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// Execute constructors.
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#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
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__do_global_ctors_1();
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#endif
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__libc_init_array();
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/* ----------------------------------Separator-----------------------------
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* After this stage, other CPU start running with the cache, however the scheduler (and ipc service) is not available.
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* Don't touch the cache/MMU until the OS is up.
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*/
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// Execute init functions of other components; blocks
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// until all cores finish (when !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE).
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do_secondary_init();
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#if SOC_CPU_CORES_NUM > 1 && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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s_system_full_inited = true;
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#endif
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esp_startup_start_app();
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ESP_INFINITE_LOOP();
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}
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