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374 lines
14 KiB
C
374 lines
14 KiB
C
/**
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/clkrst_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** SYSTEM_CPU_PERI_CLK_EN_REG register
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* register description
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*/
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#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0)
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/** SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))
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#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S)
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#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x00000001U
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#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6
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/** SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))
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#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S)
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#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001U
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#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7
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/** SYSTEM_CPU_PERI_RST_EN_REG register
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* register description
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*/
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#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4)
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/** SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1;
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* Need add description
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*/
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#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6))
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#define SYSTEM_RST_EN_ASSIST_DEBUG_M (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S)
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#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x00000001U
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#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6
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/** SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1;
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* Need add description
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*/
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#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7))
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#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S)
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#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001U
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#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7
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/** SYSTEM_CPU_PER_CONF_REG register
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* register description
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*/
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#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8)
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/** SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
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* Need add description
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*/
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#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3))
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#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
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#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U
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#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3
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/** SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000FU
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#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S)
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#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000FU
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#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4
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/** SYSTEM_MEM_PD_MASK_REG register
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* register description
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*/
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#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc)
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/** SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0))
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#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S)
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#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001U
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#define SYSTEM_LSLP_MEM_PD_MASK_S 0
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/** SYSTEM_CPU_INTR_FROM_CPU_0_REG register
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* register description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x10)
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/** SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0))
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#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S)
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#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001U
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#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0
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/** SYSTEM_CPU_INTR_FROM_CPU_1_REG register
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* register description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x14)
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/** SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0))
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#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S)
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#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001U
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#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0
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/** SYSTEM_CPU_INTR_FROM_CPU_2_REG register
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* register description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x18)
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/** SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0))
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#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S)
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#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001U
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#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0
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/** SYSTEM_CPU_INTR_FROM_CPU_3_REG register
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* register description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x1c)
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/** SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0))
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#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S)
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#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001U
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#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0
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/** SYSTEM_RSA_PD_CTRL_REG register
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* register description
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*/
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#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x20)
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/** SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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#define SYSTEM_RSA_MEM_PD (BIT(0))
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#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S)
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#define SYSTEM_RSA_MEM_PD_V 0x00000001U
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#define SYSTEM_RSA_MEM_PD_S 0
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/** SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1))
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#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S)
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#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001U
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#define SYSTEM_RSA_MEM_FORCE_PU_S 1
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/** SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
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* Need add description
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*/
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#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2))
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#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S)
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#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001U
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#define SYSTEM_RSA_MEM_FORCE_PD_S 2
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/** SYSTEM_EDMA_CTRL_REG register
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* register description
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*/
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#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x24)
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/** SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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#define SYSTEM_EDMA_CLK_ON (BIT(0))
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#define SYSTEM_EDMA_CLK_ON_M (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S)
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#define SYSTEM_EDMA_CLK_ON_V 0x00000001U
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#define SYSTEM_EDMA_CLK_ON_S 0
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/** SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define SYSTEM_EDMA_RESET (BIT(1))
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#define SYSTEM_EDMA_RESET_M (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S)
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#define SYSTEM_EDMA_RESET_V 0x00000001U
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#define SYSTEM_EDMA_RESET_S 1
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/** SYSTEM_CACHE_CONTROL_REG register
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* register description
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*/
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#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x28)
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/** SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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#define SYSTEM_ICACHE_CLK_ON (BIT(0))
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#define SYSTEM_ICACHE_CLK_ON_M (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S)
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#define SYSTEM_ICACHE_CLK_ON_V 0x00000001U
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#define SYSTEM_ICACHE_CLK_ON_S 0
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/** SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define SYSTEM_ICACHE_RESET (BIT(1))
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#define SYSTEM_ICACHE_RESET_M (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S)
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#define SYSTEM_ICACHE_RESET_V 0x00000001U
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#define SYSTEM_ICACHE_RESET_S 1
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/** SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1;
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* Need add description
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*/
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#define SYSTEM_DCACHE_CLK_ON (BIT(2))
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#define SYSTEM_DCACHE_CLK_ON_M (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S)
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#define SYSTEM_DCACHE_CLK_ON_V 0x00000001U
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#define SYSTEM_DCACHE_CLK_ON_S 2
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/** SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0;
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* Need add description
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*/
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#define SYSTEM_DCACHE_RESET (BIT(3))
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#define SYSTEM_DCACHE_RESET_M (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S)
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#define SYSTEM_DCACHE_RESET_V 0x00000001U
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#define SYSTEM_DCACHE_RESET_S 3
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/** SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
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* register description
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*/
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#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x2c)
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/** SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
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#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
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#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
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#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
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/** SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
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#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
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#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
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#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
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/** SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
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* Need add description
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*/
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#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
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#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
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#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
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#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
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/** SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
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* Need add description
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*/
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#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
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#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
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#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
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#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
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/** SYSTEM_RTC_FASTMEM_CONFIG_REG register
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* register description
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*/
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#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x30)
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/** SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0;
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* Need add description
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*/
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#define SYSTEM_RTC_MEM_CRC_START (BIT(8))
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#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S)
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#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001U
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#define SYSTEM_RTC_MEM_CRC_START_S 8
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/** SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0;
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* Need add description
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*/
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#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FFU
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#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S)
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#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FFU
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#define SYSTEM_RTC_MEM_CRC_ADDR_S 9
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/** SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047;
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* Need add description
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*/
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#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FFU
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#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S)
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#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FFU
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#define SYSTEM_RTC_MEM_CRC_LEN_S 20
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/** SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0;
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* Need add description
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*/
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#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31))
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#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S)
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#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001U
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#define SYSTEM_RTC_MEM_CRC_FINISH_S 31
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/** SYSTEM_RTC_FASTMEM_CRC_REG register
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* register description
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*/
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#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x34)
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/** SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFFU
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#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S)
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#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFFU
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#define SYSTEM_RTC_MEM_CRC_RES_S 0
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/** SYSTEM_REDUNDANT_ECO_CTRL_REG register
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* register description
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*/
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#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38)
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/** SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0))
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#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S)
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#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001U
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#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0
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/** SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1))
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#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S)
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#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001U
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#define SYSTEM_REDUNDANT_ECO_RESULT_S 1
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/** SYSTEM_CLOCK_GATE_REG register
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* register description
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*/
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#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x3c)
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/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1;
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* Need add description
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*/
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#define SYSTEM_CLK_EN (BIT(0))
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#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S)
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#define SYSTEM_CLK_EN_V 0x00000001U
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#define SYSTEM_CLK_EN_S 0
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/** SYSTEM_MEM_PVT_REG register
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* register description
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*/
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#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x40)
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/** SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3;
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* Need add description
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*/
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#define SYSTEM_MEM_PATH_LEN 0x0000000FU
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#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S)
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#define SYSTEM_MEM_PATH_LEN_V 0x0000000FU
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#define SYSTEM_MEM_PATH_LEN_S 0
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/** SYSTEM_MEM_ERR_CNT_CLR : WO; bitpos: [4]; default: 0;
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* Need add description
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*/
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#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4))
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#define SYSTEM_MEM_ERR_CNT_CLR_M (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S)
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#define SYSTEM_MEM_ERR_CNT_CLR_V 0x00000001U
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#define SYSTEM_MEM_ERR_CNT_CLR_S 4
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/** SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0;
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* Need add description
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*/
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#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5))
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#define SYSTEM_MEM_PVT_MONITOR_EN_M (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S)
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#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x00000001U
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#define SYSTEM_MEM_PVT_MONITOR_EN_S 5
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/** SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0;
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* Need add description
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*/
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#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFFU
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#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S)
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#define SYSTEM_MEM_TIMING_ERR_CNT_V 0x0000FFFFU
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#define SYSTEM_MEM_TIMING_ERR_CNT_S 6
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/** SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0;
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* Need add description
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*/
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#define SYSTEM_MEM_VT_SEL 0x00000003U
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#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S)
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#define SYSTEM_MEM_VT_SEL_V 0x00000003U
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#define SYSTEM_MEM_VT_SEL_S 22
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/** SYSTEM_REG_DATE_REG register
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* register description
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*/
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#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
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/** SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872;
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* Need add description
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*/
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#define SYSTEM_REG_DATE 0x0FFFFFFFU
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#define SYSTEM_REG_DATE_M (SYSTEM_REG_DATE_V << SYSTEM_REG_DATE_S)
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#define SYSTEM_REG_DATE_V 0x0FFFFFFFU
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#define SYSTEM_REG_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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